//参考にしたCソースは、
//http://www.fit.ac.jp/elec/7_online/lu/sample/bmp_image_proc.cpp
//です。

`define Y_SIZE 2048     // 処理できる最大画像
`define X_SIZE 2048

`define HIGH   255      //　画像の最大強度値
`define LOW      0      //　画像の最小強度値
`define LEVEL  256      //　画像の強度レベル値

module bmp_test;
parameter read_filename="3port.bmp";
parameter write_filename1="after_abc1.bmp";
parameter write_filename2="after_abc2.bmp";
parameter write_filename3="after_abc3.bmp";
parameter [7:0] INTENSITY=100;//0-255

integer  biCompression,       
      biSizeImage,
      biXPelsPerMeter,
      biYPelsPerMeter,
      biClrUsed, 
      biClrImportant;

reg [15:0]  bfType;
integer bfSize;
reg [15:0]   bfReserved1,      bfReserved2;
integer  bfOffBits;
integer  biSize,   biWidth, biHeight;
reg [15:0] biPlanes,    biBitCount;


reg [7:0] image_in [0:`Y_SIZE][0:`X_SIZE][0:2]; // 入力カラー画像配列
reg [7:0] image_out [0:`Y_SIZE][0:`X_SIZE][0:2];        //出力カラー画像配列
reg [7:0] image_bw [0:`Y_SIZE][0:`X_SIZE];              //濃淡画像配列


//********************************************
//   24Bitビットマップファイル読み込み       *
//********************************************


task readBMP(input [128*8:1] read_filename);
        integer fp;
        integer  i, j, k;
        reg [7:0] byte;
        begin   
                // ファイルオープン
                fp = $fopen(read_filename, "rb") ;//must be binary read mode
                if (!fp) begin
                        $display("readBmp: Open error!\n");
                        $finish;
                end
                $display("input file : %s\n", read_filename);

                // ヘッダー情報読み込む
                $fread(bfType,  fp);
                $fread(bfSize,  fp);
                $fread(bfReserved1, fp);
                $fread(bfReserved2, fp);
                $fread(bfOffBits,  fp);

                $fread(biSize,  fp);
                $fread(biWidth, fp);
                if (biWidth%4) begin
                        $display("Sorry, biWidth%4 must be zero in this program. Found =%d",biWidth);
                        $finish;
                end
                $fread(biHeight, fp);
                $fread(biPlanes, fp);
                $fread(biBitCount,  fp);
                if (biBitCount !=24) begin
                        $display("Sorry, biBitCount must be 24 in this program. Found=%d",biBitCount);
                        $finish;
                end
                $fread(biCompression,  fp);
                $fread(biSizeImage,  fp);
                $fread(biXPelsPerMeter, fp);
                $fread(biYPelsPerMeter, fp);
                $fread(biClrUsed,  fp);
                $fread(biClrImportant,  fp);

        // RGB画像データ読み込む
                for (i=0; i<  biHeight; i=i+1) begin
                        for (j=0; j<  biWidth; j=j+1) begin
                                for (k=0; k<3; k=k+1) begin
                                        $fread(byte,fp);
                                        image_in[biHeight-i][j][2-k]=byte;
                                end
                        end
                end
                $display("Current POS=%d",$ftell(fp));
                $fclose(fp);
        end
endtask


//******************************************************
//   24ビット-ビットマップデータをBMPファイルに出力    *
//******************************************************

task writeBMP(input [128*8:1] write_filename,input O);
        integer fp;
        integer  i, j, k;
        
        begin
        // ファイルオープン 
                fp = $fopen(write_filename, "wb");//must be binary read mode
                if (!fp) begin
                        $display("writeBmp: Open error!\n");
                        $finish;
                end
                $display("output file : %s\n", write_filename);

        // ヘッダー情報 
                $fwrite(fp,"%u",bfType);
                $fwrite(fp,"%u",bfSize);
                $fwrite(fp,"%u",bfReserved1);
                $fwrite(fp,"%u",bfReserved2);
                $fwrite(fp,"%u",bfOffBits);

                $fwrite(fp,"%u",biSize);
                $fwrite(fp,"%u",biWidth);
                $fwrite(fp,"%u",biHeight);
                $fwrite(fp,"%u",biPlanes);
                $fwrite(fp,"%u",biBitCount);
                $fwrite(fp,"%u",biCompression);
                $fwrite(fp,"%u",biSizeImage);
                $fwrite(fp,"%u",biXPelsPerMeter);
                $fwrite(fp,"%u",biYPelsPerMeter);
                $fwrite(fp,"%u",biClrUsed);
                $fwrite(fp,"%u",biClrImportant);

        // ビットマップデータ 
                for (i=0; i< biHeight; i=i+1) begin
                        for (j=0; j< biWidth; j=j+1) begin
                                for (k=0; k<3; k=k+1)  begin
                                        if (O) $fwrite(fp,"%u",image_out[biHeight-i][j][2-k]);
                                      else $fwrite(fp,"%u",image_in[biHeight-i][j][2-k]);
                                end
                        end
                end
                $display("Current WPOS=%d",$ftell(fp));
                $fclose(fp);
        end
endtask



//**********************************************
// ＲＧＢカラー画像を256諧調白黒濃淡画像へ変換 *
//**********************************************

task BMPto256BW;
        integer y, x, a;
        begin
                for (y=0; y<biHeight; y=y+1) begin
                        for (x=0; x<biWidth; x=x+1) begin
                                a =$rtoi(0.3*image_in[y][x][0] + 0.59*image_in[y][x][1] + 0.11*image_in[y][x][2]);
                                if (a<`LOW) a = `LOW;
                                if (a>`HIGH) a = `HIGH;
                                image_bw[y][x] = a;
                        end
                end
        end
endtask



//****************************************
// 白黒画像を24bitビットマップ形式に変換 *
//****************************************
task BWto24BMP;
        integer  y, x, a;
        begin
                for (y=0; y<biHeight; y=y+1) begin
                        for (x=0; x<biWidth; x=x+1) begin
                                a = image_bw[y][x];
                                image_out[y][x][0] = a;
                                image_out[y][x][1] = a;
                                image_out[y][x][2] = a;
                        end
                end
        end
        
endtask



//****************************************
// 白黒画像の２値化                      *
//****************************************
task toBinary( input [7:0] intensity);
        
        integer y, x;
        begin

                for (y=0; y<biHeight; y=y+1)begin
                        for (x=0; x<biWidth; x=x+1) begin
                                if(image_bw[y][x] >= intensity) image_bw[y][x]=`HIGH;
                                else image_bw[y][x] = `LOW;
                        end
                end
        end
endtask


initial begin

        
        //画像処理1：
        readBMP(read_filename);   // 画像の入力,RGB24ビットカラーBMP画像を配列に格納
        writeBMP(write_filename1,0);//無変換で書き込み

        //画像処理２：白黒変換
        BMPto256BW; // ＲＧＢカラー画像を白黒画像に変換
        BWto24BMP; //　単チャンネル白黒画像を３チャンネルＢＭＰ標準フォーマットへ変換
        writeBMP(write_filename2,1);            // 白黒画像出力

        //画像処理３： 2値化
        toBinary(INTENSITY);
        BWto24BMP;
        writeBMP(write_filename3,1);            // 白黒画像出力

end

endmodule

//Jan.27.2005 Refine 2
//Jan.21.2005 Refine
//Jan.19.2005 最終版　Baseband/DemodulatorのEye　生成
//                                       Coe FILE　生成

`timescale 1ps/1ps
module hard_test_bench;
//Hard パラメータ
        parameter INPUT_DATA_MSB=7;
        parameter HOST_DATA_MSB=((INPUT_DATA_MSB+1)*2-1);
        parameter OUTPUT_DATA_MSB=11;
        parameter ADDRESS_MSB=11;


//テストベンチパラメータ
        parameter real Freq =150e6*1000/999;//150MHz Carrior Frequency
        parameter real Modulation =0.01;// +-1% GFSK Modulation
        parameter integer Clock_Period=10;//10ps 10ps resolution test bench
        parameter File_Name="bessel5.txt";//System Matrix A,B,C,D file for bessl filter
                                                                      // 3dB cutoff=5MHz  
        parameter  integer Filter_Degree= 5;//System Matrix 's Degree
        parameter  integer CYCLE=Clock_Period*3*333 ;//
        parameter  integer BasebandCycle=1000*100/(Clock_Period*2);//10Mbps
        localparam integer Item_Counter_Max=2048*2-1;//4KB
        parameter integer IQ_Delay=1667;//90Degree shift at 150MHz
        parameter integer HOLD_TIME=1;

        real fc;//Carrier Frequency
        real fb;//BaseBand Frequency
        real fm;//Modulated Frequency

//rungekutta systems matrix input/output array
        real read_array[0:10];// Input vector for rungekutta
        real write_array[0:10];//Output vector from rugekutta

        real t;
        reg clock=0;
        reg signed [11:0] filt_out;//for monitoring
        
        real filt_outr;
        reg sync_reset1,sync_reset;

        real modulated_waveform;//変調波形
        reg  signed [INPUT_DATA_MSB:0] demodulator_input;//８x2ビットサンプリング信号
                                                                                                     //　復調器の入力になる
        
        real theta,delta_theta,omega;//Dec.22.2004
        
        wire NRZ;//Baseband NRZ
        wire TXD;//UART 出力
        wire signed [OUTPUT_DATA_MSB:0] demodulated_wave;//復調器出力Data
        integer fp=0;

//Hardware IF Signals
        reg clk=0;
        reg RST_In;
        
        reg  [ADDRESS_MSB:0] HOST_ADDRESS=0;
      reg [HOST_DATA_MSB:0] HOST_DATA=0;
        reg HOST_WRITE_ENABLE=0;
        wire CLKFX_OUT;
        wire dcm_clock=CLKFX_OUT;//150MHz FPGA output CLOCK
        wire  delayed_clock;
        wire  HOST_WRITE_CLOCK;

//システムシミュレーション用
        real cos_real,sin_real;
        real cos_real_z1,sin_real_z1;
        real diff_real;
        integer mag;


assign  #(HOLD_TIME) HOST_WRITE_CLOCK=delayed_clock;//RTL シミュレーション時、
                                                                                        //HOSTにIQをWriteするためのクロック
assign #(IQ_Delay) delayed_clock =  dcm_clock;//CLKFX_OUT;//CLKFX_OUTを90 度
                                                                                  //シフトした150MHz　クロック  

//テストベンチクロック　ベッセルフィルタの時間応答計算に使用するので、十分細かくする
//DCMに端数がでないように3の倍数(150/50)とすること。そうでないとジッタが発生する
        always #Clock_Period clock=~clock;

//FPGAシステムクロック 50MHz Starter　Kit仕様
        always #(CYCLE) clk=~clk;

//NRZ よりベッセルフィルタの時間応答を計算する。
//
//`define USE_ROM_DATA //ROM DATAを使うならこれをONにする
`ifndef USE_ROM_DATA //ROM DATA を使わない場合、NRZより送信変調波を作成する
                                           //　ROM　DATAを使う場合は、SIM時間短縮のため
                                           //以下は実行しない
        always @(   clock) begin//Jan.19.2005
            
              t=$time()*1e-12;

              read_array[0]=(NRZ==1 ? 1 :-1);//1/0 => 1/-1 にマッピング 
              $runge_kutta(File_Name,1);//アナログシミュレータで、ベッセルフィルタ出力計算
                filt_outr=write_array[Filter_Degree-1];//出力をREALで得る　Get filtered outout 
                filt_out=$rtoi($rint(filt_outr*1023));//フィルタ出力のモニタ用        

                fc=Freq;
                fb=Freq*Modulation*filt_outr;
                fm=fc+fb;
                omega=2.0*fm*$M_PI;
                delta_theta=(Clock_Period)*1e-12*omega;//Jan.19.2005
                theta=theta+delta_theta;
                modulated_waveform=$sin(theta);//変調した送信波　150MHz
                //量子化した、変調した送信波　150MHzオーバフロー考慮、四捨五入後、整数変換
                demodulator_input=$rtoi($rint(modulated_waveform*(  2**INPUT_DATA_MSB -1.0)));
        end
`else 

`endif

//coe file 生成
//`define MAKE_COE_FILE // XILINX　RAM　初期化ファイル生成を生成するならON
`ifdef MAKE_COE_FILE
        initial begin
                fp=$fopen("modulator_out.coe","w");
                $fwrite(fp,"memory_initialization_radix=16;\n");
                $fwrite(fp,"memory_initialization_vector=\n");
        end
`endif
        integer item_counter=0;
        integer dcm_instead_counter=0;
        integer cos_monitor;
        always @(posedge dcm_clock) begin//cos エッジ
                        #1;
                        HOST_DATA[INPUT_DATA_MSB:0]=demodulator_input;//Set  LSB WORD
                        cos_real_z1=cos_real;
                        cos_real=modulated_waveform;
                        cos_monitor=$rtoi(1000*cos_real); 
        end

        always @(posedge delayed_clock) begin//sin エッジ
                        #1;
                        HOST_DATA[HOST_DATA_MSB: INPUT_DATA_MSB+1]=demodulator_input;
                        //Set MSB WORD 
                        if (!HOST_WRITE_ENABLE) HOST_ADDRESS=0;//最初は０
                        else                                    HOST_ADDRESS=HOST_ADDRESS+1;
                        //次からインクリメント
                        
                        HOST_WRITE_ENABLE=1;//Write Start
                        sin_real_z1=sin_real;
                        sin_real=modulated_waveform;
                        diff_real=cos_real*sin_real_z1 -sin_real*cos_real_z1;
                        diff_real=diff_real*1023*16;
                        mag=$rtoi(diff_real);

`ifdef MAKE_COE_FILE // XILINX　RAM　初期化ファイル生成を生成するなら
                        if (item_counter==Item_Counter_Max)     begin//RAM 最終アドレスまで書いたら
                                                                                                //終わり
                                 $fwrite(fp,"%4h;\n",HOST_DATA);
                                 $fclose(fp);
                                 $finish;
                        end else begin
                                 $fwrite(fp,"%4h,\n",HOST_DATA);
                        end
`endif
                        item_counter=item_counter+1;
        end

//NRZ 生成
        baseband #(.counter_max(BasebandCycle)) base(clock,NRZ);//NRZ 生成 

//アイパターン生成

`define EYE_BASEBAND //ベースバンドのアイパターンを生成するとき　これをON
`define EYE_DEMODULATOR //復調器出力のアイパターンを生成するとき　これをON

`ifdef EYE_BASEBAND    
         eye_monitor #(.samples_per_scan(15*2*2),.max_columns(32) 
         ,.Eye_Save_Data_File("eye_base.txt"))  eye_base(dcm_clock,filt_out);
`endif

`ifdef EYE_DEMODULATOR
         eye_monitor #(.samples_per_scan(15*2*2),.max_columns(32)) eye_demo(dcm_clock,mag);
         //mag,demodulated_wave
`endif




//Reset
        initial begin
                        
                $runge_kutta(File_Name,0,read_array,write_array);//アナログシミュレータ
                                                                                                    //のオブジェクト初期化
                RST_In=0;
                #(10*1000);
                RST_In=1;
                #(100*1000);
                RST_In=0;

        end

//復調器
        hardware   #( .INPUT_DATA_MSB(INPUT_DATA_MSB),
                             .HOST_DATA_MSB(HOST_DATA_MSB),
                             .ADDRESS_MSB(ADDRESS_MSB),
                             .OUTPUT_DATA_MSB(OUTPUT_DATA_MSB)  )

                        dut  (  .RST_In(RST_In),//Reset
                            . CLKIN_IN(clk),//FPGA 入力CLOCK=50MHｚ
                            . HOST_CLK(HOST_WRITE_CLOCK),// 復調器RAMへWrite　入力CLOCK
                            . HOST_ADDRESS(HOST_ADDRESS),//復調器入力　RAM　Address指定
                            . HOST_WRITE_ENABLE(HOST_WRITE_ENABLE),//復調器入力Write
                            .HOST_DATA(HOST_DATA), // 復調器入力Data
                            .output_data(demodulated_wave),    //復調器出力Data
                            .CLKFX_OUT(CLKFX_OUT),//150MHz FPGA 出力
                            .TXD(TXD));//UART 出力　115.2Kbps
                                 
   
//uart read port
  wire [7:0] buffer_reg;
  wire int_req;
  localparam LF=8'h0d;//改行コード
        
        always @(posedge clk, posedge RST_In) begin
                if (RST_In) sync_reset <=1'b1;
                else sync_reset<=1'b0;
        end
        
//`define READ_GENERATED_UART_DATA //FPGA　UARTからのデータをTEXT　Save
                                                                                //=>uart.txt
//RTL とコンペアをとる場合は、コメントをトル
`ifdef READ_GENERATED_UART_DATA 
        parameter uart_file="uart.txt";//実機が出力したUART　テキストファイル
        reg  [OUTPUT_DATA_MSB:0] uart_mem [0 :4096*2-1];//実機のデータ保持メモリ
        reg signed [OUTPUT_DATA_MSB:0] uart_output;//メモリ内容を引っ張り出す
        reg  [ADDRESS_MSB+1:0]  uart_mem_address=-(13'h100a-13'h0c70);
                                                                  //垂れ流しUART　DATAの調整値
   
         initial begin
                $readmemh(uart_file,uart_mem);//uart_mem に読み込んだデータを格納
        end
        
      always @* uart_output=uart_mem[uart_mem_address];//150MHz　クロック同期
     always @(posedge   CLKFX_OUT) uart_mem_address<=uart_mem_address+1;//
`endif

   uart_read   uart_read_port( .sync_reset(sync_reset), .clk(clk)
        , .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));//実機のTX port のテスト用として

//UART からのデータを12'hｘｘｘCRで表示する
        always @(posedge int_req) begin
                begin :local
                
                        reg [7:0] local_mem [0:3];
                        integer i=0;
                        
                        if (i>=4) $stop;//Assert(0);

                        if (buffer_reg==LF) begin :local2 //pop stack
                                integer j;
                                j=0;
                                while( j < i) begin
                                        $write( "%c",local_mem[j]);
                                        j=j+1;
                                end
                                $write("     : time=%t\n",$time);
                                i=0;//clear stack       
                        end else begin//push stack
                                
                                local_mem[i]=buffer_reg;
                                i=i+1;
                         end
                end
                
        end

endmodule

//ランダムNRZを生成する
module baseband
                #(parameter counter_max=1000)
                   
                (
                        input clock,
                        output reg NRZ=1
                );

        localparam  integer MAX=counter_max-1;
        localparam integer initial_value_counts=4;//最初は、Bessel安定期間
        localparam integer finish_value_counts=counter_max-5;//最後も１にしているが、
                                                                //位相があっていないので、Wrap時にNoiseがでる。                                                         
        reg [15:0] counter=0;
        reg [15:0] baseband_counter=0;

        always @(posedge clock) begin
                if (counter==MAX) counter<=0;//10Mbps counter
                else    counter<=counter+1;
        end

      always @(posedge clock) begin
                if (counter==MAX) begin
                        baseband_counter <=baseband_counter+1;
                        if ( baseband_counter <=initial_value_counts ||
                             baseband_counter >=finish_value_counts)  NRZ<=1;
                        else NRZ<=$random %2==1;//ランダム　10Mbps NRZ

                end
        end



endmodule


//アイパターンを作る。EXCEL 読み込み用のコンマセパレート　テキストファイルを生成する
//EXCEL読み込み時に、コンマ を指定すること。
module eye_monitor #(parameter samples_per_scan=32,//行数
                                                           max_columns=64,//列数
                                                           Eye_Save_Data_File="eye_demo.txt" //ファイル名       
                                        ) 
                        (
                                input clock,
                                input signed [11:0] baseband_out
                        );
        
        
        
        integer  sample_counter=0;
        integer  column_counter=0; 
        integer fi;
        integer i,j;
        
        reg  [11:0]  saved_wave [0:samples_per_scan][0:max_columns];
        
                
        always @(posedge clock) begin
                        saved_wave[sample_counter][column_counter] =baseband_out;
                        if  (sample_counter==samples_per_scan-1)  begin
                                        sample_counter<=0;
                                        column_counter<=column_counter+1;
                                        if (column_counter==max_columns) begin
                                                save_data_to_file;
                                                $stop;
                                        end
                        end else        sample_counter <=sample_counter+1;
        end


        task save_data_to_file;
                begin
                        fi=$fopen(Eye_Save_Data_File);
                        for (i=0;i<samples_per_scan;i=i+1) begin
                                for (j=0;j< max_columns;j=j+1) begin
                                        if (j==0)               $fwrite(fi,"%d ",$signed(saved_wave[i][j]));
                                        else if (j==max_columns-1) $fdisplay(fi,", %d ",$signed(saved_wave[i][j]));
                                        else    $fwrite(fi,",%d",$signed(saved_wave[i][j]));
                                end
                        end
                        $fclose(fi);
                end
        endtask

endmodule
//Jan.27.2005 Refine

//FPGA 回路記述モジュール
//RTL シミュレーション時は、HOSTからIQをもらう　、復調出力12ビット150MHz
//実機では、内蔵ROMによりIQを生成　UART　115.2Kbps で、RAMにSaveされた復調出力を出力
//
module hardware #(parameter INPUT_DATA_MSB=7,
                                 parameter HOST_DATA_MSB=(INPUT_DATA_MSB+1)*2-1,
                                 parameter ADDRESS_MSB=11,
                                 parameter OUTPUT_DATA_MSB=11   )


                          (  input RST_In,
                             input CLKIN_IN,
                             input HOST_CLK,
                             input [ADDRESS_MSB :0] HOST_ADDRESS,
                             input HOST_WRITE_ENABLE,
                             input [HOST_DATA_MSB :0] HOST_DATA,
                             output signed [OUTPUT_DATA_MSB :0] output_data,
                             output CLKFX_OUT,
                             output TXD);
                                 
   
  reg [ADDRESS_MSB:0] address,address_d,address_dup1,address_dup2,address_dup3,address_dup4,address_dup5; 
 
  wire signed [INPUT_DATA_MSB:0] data_in1,data_in2;
 
    
//uart
   wire [ADDRESS_MSB:0] address_for_uart;
   reg sync_reset_uart;
   wire clk0;
   wire signed  [OUTPUT_DATA_MSB:0] demodulated_wave_final;     

//XilinX DCMモジュール： 50MHz システムクロックを入力　=>150MHzを出力
    mydcm dcm(.CLKIN_IN(CLKIN_IN), 
             .RST_IN(RST_In), 
             .CLKFX_OUT(CLKFX_OUT), 
             .CLKIN_IBUFG_OUT(), 
             .CLK0_OUT(clk0), 
             .LOCKED_OUT());

//復調器モジュール： 150MHz　クロックで、I/Qを入力、=>復調出力を12ビット幅で出力
 demodulator_hardware_new_sampling #(.Demo_MSB(INPUT_DATA_MSB)) demodulator( 
                        .dcm_clock(CLKFX_OUT),//
                        .async_reset(RST_In),
                        .modulated_wave_sin(data_in1),//
                        .modulated_wave_cos(data_in2),//
                        .demodulated_wave_final(demodulated_wave_final));//

//Dual Portモジュール：1２ビットｘ４KWords
//復調出力SaveのためのDual Port RAM 入力は、復調出力（１２ビット幅）=> 出力は、
//UARTに出力しないのなら、RTLシミュレーション用に150MHzで復調出力を出す
//UART選択時は、UART_CNTRLは、アドレスを制御する
//`define UART_TX_OUTPUT
        `ifndef UART_TX_OUTPUT //UART を使わないのなら

                dualram  dual_portram(
                .addra(address_dup4),
                .addrb(address_dup5),
                .clka(CLKFX_OUT),       
                .clkb(CLKFX_OUT),
                .dina(demodulated_wave_final),
                .dinb(),
                .douta(),
                .doutb(output_data),
                .wea(1'b1),//Jan.23.2005
                .web(1'b0));    // synthesis black_box

        `else//uart 出力

                dualram  dual_portram(
                .addra(address_dup4),
                .addrb(address_for_uart),
                .clka(CLKFX_OUT),
                .clkb(clk0),//uart を選択すると出力は50MHz　Clockになるので
                .dina(demodulated_wave_final),//RAM入力も50MHzサンプリングになる。
                .dinb(),
                .douta(),
                .doutb(output_data),//RAM からの出力Data
                .wea(1'b1),  //Jan.23.2005 
                .web(1'b0));    // synthesis black_box

                uart_ctrl  uart_write_port( 
                                    .ASYNC_RESET(RST_In),
                                    .clk_50M(clk0),
                                    .ram_data(output_data),
                                    .ram_address(address_for_uart),
                                    .TXD(TXD));


        `endif


//初期化付RAMモジュール：16bits（IQ)ｘ4KWords
//`define USE_ROM_DATA  //HOST から生成Dataを使う場合には、コメントアウト
//RTL シミュレーション時は、HOSTからのDATA(150MHz)をバッファリングする
//実機時は、HOST　DATAは、無視。RAM初期値を使う 

        myrom  rom(
        .addra(address_dup2),
        .addrb(HOST_ADDRESS),
        .clka(CLKFX_OUT),
        .clkb(HOST_CLK),
        .dina(),
        .dinb(HOST_DATA),
        .douta( {data_in2,data_in1}),
        .doutb( ),

        .wea(1'b0),

`ifdef USE_ROM_DATA //ROM を使うならWRITEしない
        .web(1'b0));
`else 
        .web(HOST_WRITE_ENABLE));   

`endif

        



  always @(posedge CLKFX_OUT or posedge RST_In) begin
                if (RST_In) address<=0;
                else address<=address+1;

        end
        
        always @(posedge CLKFX_OUT) address_d<=address;
        always @(posedge CLKFX_OUT) address_dup1<=address;
        always @(posedge CLKFX_OUT) address_dup2<=address_dup1;
        always @(posedge CLKFX_OUT) address_dup3<=address_dup2;
        always @(posedge CLKFX_OUT) address_dup4<=address_dup3;
        always @(posedge CLKFX_OUT) address_dup5<=address_dup4;

endmodule

//Jan.27.2005 Refine

//FM 復調器
module demodulator_hardware_new_sampling #(parameter Demo_MSB=7) ( 
                        input dcm_clock,//150MHz
                        input async_reset,
                        input signed [Demo_MSB:0] modulated_wave_sin,//150MHz
                        input signed [Demo_MSB:0] modulated_wave_cos,//150MHz
                        output signed [Demo_MSB+4:0] demodulated_wave_final);//150MHz

        reg signed [Demo_MSB:0] input_reg_sin,input_reg_cos;
        reg signed [Demo_MSB:0] sin_input,cos_input,cos_i,sin_i,cos_r,sin_r;
        reg signed [Demo_MSB:0] sin_z2,cos_z2, sin_z4,cos_z4,sin_z1,sin_z3,cos_z1,cos_z3;
        reg signed [Demo_MSB:0] sin_z5,cos_z5, sin_z6,cos_z6,sin_z7,sin_z8,cos_z7,cos_z8;

        reg signed [(Demo_MSB+1)*2-1:0] mult1,mult2;
        wire signed [(Demo_MSB+1)*2-1:0] sin_mul,cos_mul;
        wire signed [(Demo_MSB+1)*2-1:0] sin_ex_z4,cos_ex_z4;
        wire signed  [(Demo_MSB+1)*2-1:0] diff_reg;


       always @(posedge dcm_clock ) //復調器入力を一旦FFで受ける
                    input_reg_sin<=modulated_wave_sin;
         
        always @(posedge dcm_clock ) //復調器入力を一旦FFで受ける
                    input_reg_cos<=modulated_wave_cos;
         

        always @(posedge dcm_clock) begin//ディレイ　Z8まであるが、合成されるのは、Z4まで
                sin_z1<=input_reg_sin;
                sin_z2<=sin_z1;
                sin_z3<=sin_z2;
                sin_z4<=sin_z3;
                sin_z5<=sin_z4;
                sin_z6<=sin_z5;
                sin_z7<=sin_z6;
                sin_z8<=sin_z7;
                cos_z1<=input_reg_cos;
                cos_z2<=cos_z1;
                cos_z3<=cos_z2;
                cos_z4<=cos_z3;
                cos_z5<=cos_z4;
                cos_z6<=cos_z5;
                cos_z7<=cos_z6;
                cos_z8<=cos_z7;
        end

        assign sin_ex_z4=sin_z4;//アイパターン検討結果、Z4を選択
        assign cos_ex_z4=cos_z4;//アイパターン検討結果、Z4を選択

        
        always @(posedge dcm_clock ) begin
                begin
                        mult1<=input_reg_sin*cos_ex_z4;//符号付乗算器記述
                        mult2<=input_reg_cos*sin_ex_z4;//符号付乗算器記述
                end

        end

        mysub sub(//Xilinx パイプラインド減算モジュール　Coregenで生成
        .A(mult1),
        .B(mult2),
        .Q(diff_reg),
        .CLK(dcm_clock));    // synthesis black_box

        assign demodulated_wave_final=diff_reg[Demo_MSB+4+2:2];//復調器出力
endmodule

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200pq208-4 

 Number of Slices:                      72  out of   1920     3%  
 Number of Slice Flip Flops:           126  out of   3840     3%  
 Number of 4 input LUTs:                98  out of   3840     2%  
 Number of bonded IOBs:                 21  out of    141    14%  
 Number of MULT18X18s:                   2  out of     12    16%  
 Number of GCLKs:                        1  out of      8    12%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
dcm_clock                          | BUFGP                  | 144   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 4.179ns (Maximum Frequency: 239.292MHz)
   Minimum input arrival time before clock: 2.373ns
   Maximum output required time after clock: 6.172ns
   Maximum combinational path delay: No path found

//Jan20.2005 115.Kbps に調整
//Jan.19.2005
//uart control  仕様
// 50MHz Clockで動く
// 12bit RAM をUARTでダンプする
// 50MHz sync_reset を出力
// ダンプは　ASYNC_RESETを抜けたら、２CLOCK　WAITしした後　RAM　を上位４BITからアクセス
// HEX で出力　　　ABCLF　LF=0Aで４DIGIT単位に出力
// 4KADDRESS は、ラップするとき、０Aを出す
// =>  50M CLOCK
// =>  ASYNC_RESET
//                            => RAM_ADDRESS[11:0] 
//                                  <=  RAM_DATA　　[11:0]
//                                      => TXD
//                                      
//
//


module uart_ctrl(       input ASYNC_RESET,
                                input clk_50M,
                                input wire [11:0]       ram_data,
                                output reg [11:0] ram_address,
                                output TXD);

        parameter [7:0] CR=8'h0d;
        reg sync_reset1,sync_reset2,sync_reset;
        reg [3:0] state;
        wire busy;

//monitor address
  always @* $display("UART RAM_ADDRESS=%h",ram_address);


//combinatial logics
        reg write_request;
        reg [7:0] set_data;

        always @(posedge clk_50M, posedge ASYNC_RESET) begin
                if (ASYNC_RESET) sync_reset1<=1;
                else    sync_reset1 <=0;                                
        end

        always @(posedge clk_50M) sync_reset2<=sync_reset1;
        always @(posedge clk_50M) sync_reset <=sync_reset2;

        localparam idle_state=4'b0000,
                           state1=4'b0001,
                           uart_set_msb=4'b0010,
                           waiting_msb_write_done=4'b0011,
                           uart_set_middle=4'b0100,
                           waiting_middle_write_done=4'b0101,
                           uart_set_lsb=4'b0110,
                           waiting_lsb_write_done=4'b0111,
                           uart_set_lf=4'b1000,
                           address_check_state=4'b1001,
                           waiting_lf_write_done=4'b1010,
                           address_inc_state=4'b1011,
                           state12=4'b1100;

//state machine
        always @(posedge clk_50M) begin
                if (sync_reset)  state <=0;
                else case (state)
                        idle_state: state<=state1;
                        state1: if (busy) ;//wait
                                    else state <=uart_set_msb;
                        uart_set_msb: state <=waiting_msb_write_done;
                        waiting_msb_write_done: if (busy);//wait
                                    else state <=uart_set_middle;
                        uart_set_middle:  state <=waiting_middle_write_done;
                        waiting_middle_write_done: if (busy);//wait
                                    else state <=uart_set_lsb;                          
                        uart_set_lsb:  state <=waiting_lsb_write_done;
                        waiting_lsb_write_done: if (busy);//wait
                                    else state <=uart_set_lf;
                        uart_set_lf:  state <=address_check_state;
                        address_check_state: state<=waiting_lf_write_done;      //if (address_last) uart_set
                        waiting_lf_write_done: if (busy);//wait
                                        else state <=address_inc_state;
                        address_inc_state: state<=idle_state;
                        default : state <=idle_state;
                endcase
        end

//ram address
        always @(posedge clk_50M) begin
                if (sync_reset) ram_address<=0;
                else if (state==address_inc_state) ram_address <=ram_address+1;
        end

//uart
        uart_write   uw( .sync_reset(sync_reset),
                                    .clk(clk_50M),
                                    .txd(TXD),
                                    .data_in(set_data) ,
                                    .write_request(write_request),
                                    .write_done(),
                                    .write_busy(busy));
        
//combinational logic
        //write_request
        always @* begin
                case (state) 
                        uart_set_msb,uart_set_middle,uart_set_lsb,uart_set_lf: write_request=1;//uart set
                        address_check_state: if (ram_address==12'hfff) write_request=1;//wrap address
                                                             else write_request=0;
                        default:write_request=0;
                endcase
        end     
        //set_data
        always @* begin
                case (state) 
                        uart_set_msb:  set_data=num_to_ascii(ram_data[ 11:8]);
                        uart_set_middle:set_data=num_to_ascii(ram_data[ 7:4]);
                        uart_set_lsb: set_data=num_to_ascii(ram_data[ 3:0]);
                        address_check_state:set_data=CR;//Jan.24.2005 wrap address
                        uart_set_lf:   set_data=CR;//Jan.24.2005
                        default :set_data=8'hxx;
                endcase 
        end     

        //digit to ascii code
        function [7:0] num_to_ascii (input [3:0] num);
                begin
                        if (num<=9) num_to_ascii=num+8'h30;
                        else        num_to_ascii=num+55;// 41hex =>A  decimal65=A   a=>10
                end
        endfunction
endmodule



//YACC から持ってきた。
module  uart_write( sync_reset, clk, txd, data_in , write_request,write_done,write_busy);
        input sync_reset,clk;
        input [7:0] data_in;
        input write_request;
        output txd,write_done;
        output write_busy;
        parameter MAX_DEPTH=7;
        parameter ADDRESS_MSB=2;
        
      reg [7:0]     queue[0:MAX_DEPTH];     
        reg [ADDRESS_MSB:0]     wpointer,rpointer;
        reg [ADDRESS_MSB+1:0]     queue_counter;
        wire            queue_full;
        wire    queing, read_request;
        wire [7:0] queue_data;
        reg read_request_ff;
        






        reg             [8:0] clk_ctr;
        reg             [2:0] bit_ctr;
        reg             [2:0] ua_state;
        reg             [7:0] tx_sr;
        reg             write_done_n;
        reg             txd;

        wire     clk_ctr_equ15, clk_ctr_equ31,  bit_ctr_equ7,
                           clk_ctr_enable_state, bit_ctr_enable_state  ;
        wire    tx_state;



        always @ (posedge clk) begin
                if (sync_reset) begin
                                wpointer <=0;

                end else if (write_request) begin
                                queue[wpointer]<=data_in;
                                wpointer <=wpointer+1;
                end 
        end

        always @ (posedge clk) begin
                if (sync_reset) read_request_ff<=1'b0;
                else                    read_request_ff<=read_request;
        end

        always @ (posedge clk) begin
                if (sync_reset) begin
                                rpointer <=0;
                end else if (read_request_ff) begin
                                rpointer <=rpointer+1;
                end 
        end


        always @ (posedge clk) begin
                if (sync_reset) begin
                                queue_counter <=000;    
                end else if (!read_request_ff && write_request) begin
                                queue_counter <=queue_counter+1;
                end else if ( read_request_ff && !write_request) begin
                                queue_counter <=queue_counter-1;
                end
        end


        assign queue_full        = (queue_counter == MAX_DEPTH+1);
        assign queing=            queue_counter !=000;
        assign read_request      = queing && ua_state==3'b000;
        assign queue_data         =queue[rpointer];

        assign write_done=ua_state==3'b101;

        assign write_busy=queue_full;
        







        always @(posedge clk ) begin
                if (sync_reset)
                        clk_ctr <= 0;
                else if (clk_ctr_enable_state && clk_ctr_equ31)  clk_ctr<=0;    
                else if (clk_ctr_enable_state)                   clk_ctr <= clk_ctr + 1;
                else    clk_ctr <= 0;
        end










        assign  clk_ctr_equ15 = clk_ctr== 216; //orig 206 
        assign  clk_ctr_equ31 = clk_ctr== 433;//413     




        
        always @(posedge clk) begin
                if (sync_reset)
                        bit_ctr <= 0;
                else if (bit_ctr_enable_state) begin
                        if (clk_ctr_equ15)
                                bit_ctr <= bit_ctr + 1;
                end
                else
                        bit_ctr <= 0;
        end

        assign  bit_ctr_equ7 = (bit_ctr==7);



        assign  clk_ctr_enable_state = bit_ctr_enable_state ||  ua_state==3'b001 ||  ua_state==3'b100 ;
        assign  bit_ctr_enable_state =  ua_state==3'b010 || ua_state==3'b011;


        always @(posedge clk ) begin
                if (sync_reset) ua_state <= 3'b000;
                else begin
                        case (ua_state)
                                3'b000: if (queing)  ua_state <= 3'b001;        
                                3'b001: if ( clk_ctr_equ15) ua_state <= 3'b010; 
                                3'b010: if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'b011;           
                                3'b011: if (clk_ctr_equ15) ua_state <= 3'b100;                                  
                                3'b100: if (clk_ctr_equ15) ua_state <= 3'b101;  
                                3'b101:  ua_state <= 3'h0;      
                                default: ua_state <= 3'h0;
                        endcase
                end
        end













        always @(posedge clk ) begin
                if (sync_reset) tx_sr<=0;
                else if (read_request_ff) tx_sr <= queue_data[7:0]; 
                else if (tx_state ) tx_sr <= {1'b0, tx_sr[7:1]};
        end
        
        assign  tx_state=(  ua_state==3'h2 || ua_state==3'h3)           &&      clk_ctr_equ15;



        always @(posedge clk ) begin
                if (sync_reset) txd <=1'b1;
                else if (sync_reset)                      txd<=1'b1;
                else if (ua_state==3'h0)                  txd<=1'b1;
                else if (ua_state==3'h1 && clk_ctr_equ15) txd<=1'b0;    
                else if (ua_state==3'h2 && clk_ctr_equ15) txd<=tx_sr[0];
                else if (ua_state==3'h3 && clk_ctr_equ15) txd<=1'b1;     
        end
endmodule

//以下はUART専用テストベンチ
//`define UART_CTRL_TEST  //UART RTLテスト時だけ、その他はコメントアウトのこと
//UART RTL テスト時は、単独ファイルで可
`ifdef UART_CTRL_TEST

module uart_ctrl_test;
        parameter CR=8'h0d;
        reg ASYNC_RESET=0;
        reg clk_50M=0;
        reg [11:0] ram_data=0;
        wire [11:0] ram_address;
        wire TXD;
        wire RXD;
        wire [7:0] buffer_reg;
        wire int_req;

        always #10 clk_50M =~clk_50M;

        always  @* ram_data=ram_address;
        initial begin
                        #1 ASYNC_RESET=1;
                        #105 ASYNC_RESET=0;
                        $display("UART WRITE PORT Test Using UART READ PORT.");
        end
                        

         uart_ctrl  uart_write_port( ASYNC_RESET,
                                    clk_50M,
                                    ram_data,
                                    ram_address,
                                    TXD);

         reg sync_reset;

        always @(posedge clk_50M ,posedge ASYNC_RESET )
                if (ASYNC_RESET)  sync_reset<=1'b1;
                else sync_reset<=1'b0; 

      uart_read   uart_read_port( .sync_reset(sync_reset), .clk(clk_50M), .rxd(TXD),.buffer_reg(buffer_reg), .int_req(int_req));

        always @(posedge int_req) begin
                begin :local
                        reg [7:0] local_mem [0:3];
                        integer i=0;
                        
                        if (i>=4) $stop;//Assert(0);

                        if (buffer_reg==CR) begin :local2 //pop stack
                                integer j;
                                j=0;
                                while( j < i) begin
                                        $write( "%c",local_mem[j]);
                                        j=j+1;
                                end
                                $write("     : time=%t\n",$time);
                                i=0;//clear stack       
                        end else begin//push stack
                                
                                local_mem[i]=buffer_reg;
                                i=i+1;
                         end
                end
                
        end

endmodule





`endif



module  uart_read( sync_reset, clk, rxd,buffer_reg, int_req);
        input sync_reset;
        input   clk, rxd;
        output  [7:0] buffer_reg;
        output  int_req;
        

//________|-|______int_req (This module,, posedge interrupt)
//
//Spec. Upper module must service within 115.2Kbpsx8bit time. Maybe enough time..hom.
//
//No error handling (overrun ) is supported.
        localparam COUNTER_VALUE1 = 216;//207
        localparam COUNTER_VALUE2 =COUNTER_VALUE1*2+1;//415
        localparam COUNTER_VALUE3 =COUNTER_VALUE1+3;//210

        reg             rxq1;
        reg             [8:0] clk_ctr;
        reg             [2:0] bit_ctr;
        reg             [2:0] ua_state;
        reg             [7:0] rx_sr;             //.,tx_sr;
        reg             int_req;
        reg             [7:0] buffer_reg;       

        wire     clk_ctr_equ15, clk_ctr_equ31, bit_ctr_equ7, 
                           clk_ctr_enable_state, bit_ctr_enable_state  ;
        wire    clk_ctr_equ0;
            

        
         
//sync_reset

//synchronization
        always @(posedge clk ) begin
                rxq1 <=rxd ;
        end
        
// 7bit counter
        always @(posedge clk ) begin
                if (sync_reset)
                        clk_ctr <= 0;
                else if (clk_ctr_enable_state && clk_ctr_equ31)  clk_ctr<=0;    
                else if (clk_ctr_enable_state)                   clk_ctr <= clk_ctr + 1;
                else    clk_ctr <= 0;
        end


// When clock is 24MHz ,followings should be set Do not forget to change simulation file too.
        assign  clk_ctr_equ15 =  (clk_ctr==COUNTER_VALUE1)  ;  // 416/2-1   Feb.9
        assign  clk_ctr_equ31 =  (clk_ctr==COUNTER_VALUE2) ;    // 416-1     Feb.9
        assign  clk_ctr_equ0=    (clk_ctr==COUNTER_VALUE3);     // for write strobe  Feb.9


        // 3bit counter
        always @(posedge clk) begin
                if (sync_reset)
                        bit_ctr <= 0;
                else if (bit_ctr_enable_state) begin
                        if (clk_ctr_equ15)
                                bit_ctr <= bit_ctr + 1;
                end
                else
                        bit_ctr <= 0;
        end

        assign  bit_ctr_equ7 = (bit_ctr==7);

        
        assign  clk_ctr_enable_state =  ua_state !=3'b000  && ua_state<=3'b011;
        assign  bit_ctr_enable_state = ua_state==3'h2;

//      
        always @(posedge clk ) begin
                if (sync_reset) ua_state <= 3'h0;
                else begin
                        case (ua_state)
                                3'h0:   if (rxq1==0) ua_state <= 3'h1;  // if rxd==0 then goto next state and enable clock                                              // start bit search
                                3'h1:   if (clk_ctr_equ15) ua_state <= 3'h2;                                    // start bit receive
                                3'h2:   if (bit_ctr_equ7 & clk_ctr_equ15) ua_state <= 3'h3;     
                                3'h3:   if (clk_ctr_equ15)     ua_state <=3'h4;                                                                 // stop bit receive
                                3'h4:   ua_state <= 3'b000;
                                default: ua_state <= 3'b000;                    
                        endcase
                end
        end


//reg_we
        always @(posedge clk ) begin
                if (sync_reset)                            buffer_reg<=8'h00;
                else if (ua_state==3'h3 && clk_ctr_equ0)  buffer_reg<=rx_sr;
        end

//int_req
        always @(posedge clk ) begin
                if (sync_reset)                             int_req<=1'b0;
//              else if (ua_state==3'h3 && clk_ctr_equ15)   int_req<=1'b1;
                else if (ua_state==3'h4 )                   int_req<=1'b1;      //Feb.1 After buffer_reg_set
                else                                        int_req<=1'b0;
        end


// rx shift reg.
        always @(posedge clk ) begin
                if (sync_reset) rx_sr <= 0;
                else if (clk_ctr_equ15) rx_sr <= {rxq1, rx_sr[7:1]};
        end
        
endmodule

------------------------------------------------------------------------
-- File         SQRT36.vhd                                            --
-- Entity       SQRT36                                                --
-- rev date     coded contents                                        --
-- 001 98/06/10 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all;
use IEEE.std_logic_arith.all;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity SQRT36 is
port(
        X       : in    std_logic_vector(35 downto 0) ; -- Input(36bit)
        Z       : out   std_logic_vector(17 downto 0)   -- Output(18bit)
    );
end SQRT36 ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of SQRT36 is

begin
--------------------------------
-- Square Root
--------------------------------
SQRT_LOOP   : process( X )
        variable    R : std_logic_vector(35 downto 0);  -- Remain
        variable    S : std_logic_vector(17 downto 0);  -- Result
        variable    T : std_logic_vector(35 downto 0);  -- Calclate Value
    begin
        -- Initialize value
        R := X ;
        -- Calculate MSB(bit 17)
        if( R(35 downto 34) >= "01" ) then
            S(17) := '1' ;
            R(35 downto 34) := R(35 downto 34) - "01" ;
        else
            S(17) := '0' ;
            R(35 downto 34) := R(35 downto 34) ;
        end if;
        -- Calculate 2nd bit(bit 16)
        T(35 downto 32) := '0' & S(17) & "01" ;
        if( R(35 downto 32) >= T(35 downto 32) ) then
            S(16) := '1' ;
            R(35 downto 32) := R(35 downto 32) - T(35 downto 32) ;
        else
            S(16) := '0' ;
        end if;
        -- Calculate 3rd bit(bit 15)
        T(35 downto 30) := '0' & T(35 downto 34) & S(16) & "01" ;
        if( R(35 downto 30) >= T(35 downto 30) ) then
            S(15) := '1' ;
            R(35 downto 30) := R(35 downto 30) - T(35 downto 30) ;
        else
            S(15) := '0' ;
        end if;
        -- Calculate 4th bit(bit 14)
        T(35 downto 28) := '0' & T(35 downto 32) & S(15) & "01" ;
        if( R(35 downto 28) >= T(35 downto 28) ) then
            S(14) := '1' ;
            R(35 downto 28) := R(35 downto 28) - T(35 downto 28) ;
        else
            S(14) := '0' ;
        end if;
        -- Calculate bit 13
        T(35 downto 26) := '0' & T(35 downto 30) & S(14) & "01" ;
        if( R(35 downto 26) >= T(35 downto 26) ) then
            S(13) := '1' ;
            R(35 downto 26) := R(35 downto 26) - T(35 downto 26) ;
        else
            S(13) := '0' ;
        end if;
        -- Calculate bit 12
        T(35 downto 24) := '0' & T(35 downto 28) & S(13) & "01" ;
        if( R(35 downto 24) >= T(35 downto 24) ) then
            S(12) := '1' ;
            R(35 downto 24) := R(35 downto 24) - T(35 downto 24) ;
        else
            S(12) := '0' ;
        end if;
        -- Calculate bit 11
        T(35 downto 22) := '0' & T(35 downto 26) & S(12) & "01" ;
        if( R(35 downto 22) >= T(35 downto 22) ) then
            S(11) := '1' ;
            R(35 downto 22) := R(35 downto 22) - T(35 downto 22) ;
        else
            S(11) := '0' ;
        end if;
        -- Calculate bit 10
        T(35 downto 20) := '0' & T(35 downto 24) & S(11) & "01" ;
        if( R(35 downto 20) >= T(35 downto 20) ) then
            S(10) := '1' ;
            R(35 downto 20) := R(35 downto 20) - T(35 downto 20) ;
        else
            S(10) := '0' ;
        end if;
        -- Calculate bit 9
        T(35 downto 18) := '0' & T(35 downto 22) & S(10) & "01" ;
        if( R(35 downto 18) >= T(35 downto 18) ) then
            S(9) := '1' ;
            R(35 downto 18) := R(35 downto 18) - T(35 downto 18) ;
        else
            S(9) := '0' ;
        end if;
        -- Calculate bit 8
        T(35 downto 16) := '0' & T(35 downto 20) & S(9) & "01" ;
        if( R(35 downto 16) >= T(35 downto 16) ) then
            S(8) := '1' ;
            R(35 downto 16) := R(35 downto 16) - T(35 downto 16) ;
        else
            S(8) := '0' ;
        end if;
        -- Calculate bit 7
        T(35 downto 14) := '0' & T(35 downto 18) & S(8) & "01" ;
        if( R(35 downto 14) >= T(35 downto 14) ) then
            S(7) := '1' ;
            R(35 downto 14) := R(35 downto 14) - T(35 downto 14) ;
        else
            S(7) := '0' ;
        end if;
        -- Calculate bit 6
        T(35 downto 12) := '0' & T(35 downto 16) & S(7) & "01" ;
        if( R(35 downto 12) >= T(35 downto 12) ) then
            S(6) := '1' ;
            R(35 downto 12) := R(35 downto 12) - T(35 downto 12) ;
        else
            S(6) := '0' ;
        end if;
        -- Calculate bit 5
        T(35 downto 10) := '0' & T(35 downto 14) & S(6) & "01" ;
        if( R(35 downto 10) >= T(35 downto 10) ) then
            S(5) := '1' ;
            R(35 downto 10) := R(35 downto 10) - T(35 downto 10) ;
        else
            S(5) := '0' ;
        end if;
        -- Calculate bit 4
        T(35 downto 8) := '0' & T(35 downto 12) & S(5) & "01" ;
        if( R(35 downto 8) >= T(35 downto 8) ) then
            S(4) := '1' ;
            R(35 downto 8) := R(35 downto 8) - T(35 downto 8) ;
        else
            S(4) := '0' ;
        end if;
        -- Calculate bit 3
        T(35 downto 6) := '0' & T(35 downto 10) & S(4) & "01" ;
        if( R(35 downto 6) >= T(35 downto 6) ) then
            S(3) := '1' ;
            R(35 downto 6) := R(35 downto 6) - T(35 downto 6) ;
        else
            S(3) := '0' ;
        end if;
        -- Calculate bit 2
        T(35 downto 4) := '0' & T(35 downto 8) & S(3) & "01" ;
        if( R(35 downto 4) >= T(35 downto 4) ) then
            S(2) := '1' ;
            R(35 downto 4) := R(35 downto 4) - T(35 downto 4) ;
        else
            S(2) := '0' ;
        end if;
        -- Calculate bit 1
        T(35 downto 2) := '0' & T(35 downto 6) & S(2) & "01" ;
        if( R(35 downto 2) >= T(35 downto 2) ) then
            S(1) := '1' ;
            R(35 downto 2) := R(35 downto 2) - T(35 downto 2) ;
        else
            S(1) := '0' ;
        end if;
        -- Calculate bit 0
        T(35 downto 0) := '0' & T(35 downto 4) & S(1) & "01" ;
        if( R(35 downto 0) >= T(35 downto 0) ) then
            S(0) := '1' ;
            R(35 downto 0) := R(35 downto 0) - T(35 downto 0) ;
        else
            S(0) := '0' ;
        end if;
        -- Result
        Z <= S ;
    end process ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// File         SQRT36.vhd                                            --
// Entity       SQRT36                                                --
// rev date     coded contents                                        --
// 001 98/06/10 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)


module  sqrt36 ( x, z );
    
    input [35:0]  x ;
    output [17:0]  z ;


    reg [35:0] sqrt_loop__r;
    reg [17:0] sqrt_loop__s;
    reg [35:0] sqrt_loop__t;
    reg [17:0] z;


    
       
   always @ (x ) begin
           sqrt_loop__r = x;
           if ((sqrt_loop__r[35:34] >= 2'b01)) 
               begin 
                   sqrt_loop__s[17] = 1'b1;
                   sqrt_loop__r[35:34] = (sqrt_loop__r[35:34] - 2'b01);
               end
               
           else 
               begin 
                   sqrt_loop__s[17] = 1'b0;
                   sqrt_loop__r[35:34] = sqrt_loop__r[35:34];
               end
               
           sqrt_loop__t[35:32] = {{1'b0,sqrt_loop__s[17]},2'b01};
           if ((sqrt_loop__r[35:32] >= sqrt_loop__t[35:32])) 
               begin 
                   sqrt_loop__s[16] = 1'b1;
                   sqrt_loop__r[35:32] = (sqrt_loop__r[35:32] - sqrt_loop__t[35:32]);
               end
               
           else 
               sqrt_loop__s[16] = 1'b0;
               
           sqrt_loop__t[35:30] = {{{1'b0,sqrt_loop__t[35:34]},sqrt_loop__s[16]},2'b01};
           if ((sqrt_loop__r[35:30] >= sqrt_loop__t[35:30])) 
               begin 
                   sqrt_loop__s[15] = 1'b1;
                   sqrt_loop__r[35:30] = (sqrt_loop__r[35:30] - sqrt_loop__t[35:30]);
               end
               
           else 
               sqrt_loop__s[15] = 1'b0;
               
           sqrt_loop__t[35:28] = {{{1'b0,sqrt_loop__t[35:32]},sqrt_loop__s[15]},2'b01};
           if ((sqrt_loop__r[35:28] >= sqrt_loop__t[35:28])) 
               begin 
                   sqrt_loop__s[14] = 1'b1;
                   sqrt_loop__r[35:28] = (sqrt_loop__r[35:28] - sqrt_loop__t[35:28]);
               end
               
           else 
               sqrt_loop__s[14] = 1'b0;
               
           sqrt_loop__t[35:26] = {{{1'b0,sqrt_loop__t[35:30]},sqrt_loop__s[14]},2'b01};
           if ((sqrt_loop__r[35:26] >= sqrt_loop__t[35:26])) 
               begin 
                   sqrt_loop__s[13] = 1'b1;
                   sqrt_loop__r[35:26] = (sqrt_loop__r[35:26] - sqrt_loop__t[35:26]);
               end
               
           else 
               sqrt_loop__s[13] = 1'b0;
               
           sqrt_loop__t[35:24] = {{{1'b0,sqrt_loop__t[35:28]},sqrt_loop__s[13]},2'b01};
           if ((sqrt_loop__r[35:24] >= sqrt_loop__t[35:24])) 
               begin 
                   sqrt_loop__s[12] = 1'b1;
                   sqrt_loop__r[35:24] = (sqrt_loop__r[35:24] - sqrt_loop__t[35:24]);
               end
               
           else 
               sqrt_loop__s[12] = 1'b0;
               
           sqrt_loop__t[35:22] = {{{1'b0,sqrt_loop__t[35:26]},sqrt_loop__s[12]},2'b01};
           if ((sqrt_loop__r[35:22] >= sqrt_loop__t[35:22])) 
               begin 
                   sqrt_loop__s[11] = 1'b1;
                   sqrt_loop__r[35:22] = (sqrt_loop__r[35:22] - sqrt_loop__t[35:22]);
               end
               
           else 
               sqrt_loop__s[11] = 1'b0;
               
           sqrt_loop__t[35:20] = {{{1'b0,sqrt_loop__t[35:24]},sqrt_loop__s[11]},2'b01};
           if ((sqrt_loop__r[35:20] >= sqrt_loop__t[35:20])) 
               begin 
                   sqrt_loop__s[10] = 1'b1;
                   sqrt_loop__r[35:20] = (sqrt_loop__r[35:20] - sqrt_loop__t[35:20]);
               end
               
           else 
               sqrt_loop__s[10] = 1'b0;
               
           sqrt_loop__t[35:18] = {{{1'b0,sqrt_loop__t[35:22]},sqrt_loop__s[10]},2'b01};
           if ((sqrt_loop__r[35:18] >= sqrt_loop__t[35:18])) 
               begin 
                   sqrt_loop__s[9] = 1'b1;
                   sqrt_loop__r[35:18] = (sqrt_loop__r[35:18] - sqrt_loop__t[35:18]);
               end
               
           else 
               sqrt_loop__s[9] = 1'b0;
               
           sqrt_loop__t[35:16] = {{{1'b0,sqrt_loop__t[35:20]},sqrt_loop__s[9]},2'b01};
           if ((sqrt_loop__r[35:16] >= sqrt_loop__t[35:16])) 
               begin 
                   sqrt_loop__s[8] = 1'b1;
                   sqrt_loop__r[35:16] = (sqrt_loop__r[35:16] - sqrt_loop__t[35:16]);
               end
               
           else 
               sqrt_loop__s[8] = 1'b0;
               
           sqrt_loop__t[35:14] = {{{1'b0,sqrt_loop__t[35:18]},sqrt_loop__s[8]},2'b01};
           if ((sqrt_loop__r[35:14] >= sqrt_loop__t[35:14])) 
               begin 
                   sqrt_loop__s[7] = 1'b1;
                   sqrt_loop__r[35:14] = (sqrt_loop__r[35:14] - sqrt_loop__t[35:14]);
               end
               
           else 
               sqrt_loop__s[7] = 1'b0;
               
           sqrt_loop__t[35:12] = {{{1'b0,sqrt_loop__t[35:16]},sqrt_loop__s[7]},2'b01};
           if ((sqrt_loop__r[35:12] >= sqrt_loop__t[35:12])) 
               begin 
                   sqrt_loop__s[6] = 1'b1;
                   sqrt_loop__r[35:12] = (sqrt_loop__r[35:12] - sqrt_loop__t[35:12]);
               end
               
           else 
               sqrt_loop__s[6] = 1'b0;
               
           sqrt_loop__t[35:10] = {{{1'b0,sqrt_loop__t[35:14]},sqrt_loop__s[6]},2'b01};
           if ((sqrt_loop__r[35:10] >= sqrt_loop__t[35:10])) 
               begin 
                   sqrt_loop__s[5] = 1'b1;
                   sqrt_loop__r[35:10] = (sqrt_loop__r[35:10] - sqrt_loop__t[35:10]);
               end
               
           else 
               sqrt_loop__s[5] = 1'b0;
               
           sqrt_loop__t[35:8] = {{{1'b0,sqrt_loop__t[35:12]},sqrt_loop__s[5]},2'b01};
           if ((sqrt_loop__r[35:8] >= sqrt_loop__t[35:8])) 
               begin 
                   sqrt_loop__s[4] = 1'b1;
                   sqrt_loop__r[35:8] = (sqrt_loop__r[35:8] - sqrt_loop__t[35:8]);
               end
               
           else 
               sqrt_loop__s[4] = 1'b0;
               
           sqrt_loop__t[35:6] = {{{1'b0,sqrt_loop__t[35:10]},sqrt_loop__s[4]},2'b01};
           if ((sqrt_loop__r[35:6] >= sqrt_loop__t[35:6])) 
               begin 
                   sqrt_loop__s[3] = 1'b1;
                   sqrt_loop__r[35:6] = (sqrt_loop__r[35:6] - sqrt_loop__t[35:6]);
               end
               
           else 
               sqrt_loop__s[3] = 1'b0;
               
           sqrt_loop__t[35:4] = {{{1'b0,sqrt_loop__t[35:8]},sqrt_loop__s[3]},2'b01};
           if ((sqrt_loop__r[35:4] >= sqrt_loop__t[35:4])) 
               begin 
                   sqrt_loop__s[2] = 1'b1;
                   sqrt_loop__r[35:4] = (sqrt_loop__r[35:4] - sqrt_loop__t[35:4]);
               end
               
           else 
               sqrt_loop__s[2] = 1'b0;
               
           sqrt_loop__t[35:2] = {{{1'b0,sqrt_loop__t[35:6]},sqrt_loop__s[2]},2'b01};
           if ((sqrt_loop__r[35:2] >= sqrt_loop__t[35:2])) 
               begin 
                   sqrt_loop__s[1] = 1'b1;
                   sqrt_loop__r[35:2] = (sqrt_loop__r[35:2] - sqrt_loop__t[35:2]);
               end
               
           else 
               sqrt_loop__s[1] = 1'b0;
               
           sqrt_loop__t[35:0] = {{{1'b0,sqrt_loop__t[35:4]},sqrt_loop__s[1]},2'b01};
           if ((sqrt_loop__r[35:0] >= sqrt_loop__t[35:0])) 
               begin 
                   sqrt_loop__s[0] = 1'b1;
                   sqrt_loop__r[35:0] = (sqrt_loop__r[35:0] - sqrt_loop__t[35:0]);
               end
               
           else 
               sqrt_loop__s[0] = 1'b0;
               
           z <= sqrt_loop__s;
   end //always
    

endmodule

------------------------------------------------------------------------
-- File         DIV18.vhd                                             --
-- Entity       DIV18                                                 --
-- rev date     coded contents                                        --
-- 001 98/06/23 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_arith.all;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity DIV18 is
port(
        X       : in    std_logic_vector(17 downto 0) ; -- Input(18bit)
        Y       : in    std_logic_vector(17 downto 0) ; -- Input(18bit)
        C       : out   std_logic ;                     -- OverFlow Flag
        Z       : out   std_logic_vector(17 downto 0)   -- Output(18bit)
    );
end DIV18 ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of DIV18 is

begin
--------------------------------
-- X divide by Y (X < Y)
--------------------------------
DIVIDE_LOOP     : process( X, Y )
        variable    R : std_logic_vector(19 downto 0);  -- Remain
        variable    S : std_logic_vector(17 downto 0);  -- Result
        variable    T : std_logic_vector(19 downto 0);  -- Temporaly
    begin
        if( X < Y ) then
            -- Initialize value
            R := '0' & X & '0' ;    -- R = 2 * X
            T := "00" & Y ;         -- T = Y
            for i in 17 downto 0 loop
                if( R >= T ) then
                    S(i) := '1' ;
                    R := R - T ;
                else
                    S(i) := '0' ;
                end if ;
                R := R(18 downto 0) & '0' ;
            end loop ;
            -- Result
            Z <= S ;
            C <= '0' ;
        else
            C <= '1' ;
            Z <= "000000000000000000" ;
        end if ;
    end process ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// File         DIV18.vhd                                             --
// Entity       DIV18                                                 --
// rev date     coded contents                                        --
// 001 98/06/23 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  div18 ( x, y, c, z );
    
    input [17:0]  x ;
    input [17:0]  y ;
    output c;
    output [17:0]  z ;


    reg [19:0] divide_loop__r;
    reg [17:0] divide_loop__s;
    reg [19:0] divide_loop__t;
    reg c;
    reg [17:0] z;


    
       
   always @ (x or y ) begin
           if ((x < y)) 
               begin 
                   divide_loop__r = {{1'b0,x},1'b0};
                   divide_loop__t = {2'b00,y};
                   begin :Block_Name_1
                       integer i;
                       for (i=17;i>=0;i=i-1) begin 
                           begin 
                               if ((divide_loop__r >= divide_loop__t)) 
                                   begin 
                                       divide_loop__s[i] = 1'b1;
                                       divide_loop__r = (divide_loop__r - divide_loop__t);
                                   end
                                   
                               else 
                                   divide_loop__s[i] = 1'b0;
                                   
                               
                               divide_loop__r = {divide_loop__r[18:0],1'b0};
                           end
                           
                       end //for
                   end //end Block
                   z <= divide_loop__s;
                   c <= 1'b0;
               end
               
           else 
               begin 
                   c <= 1'b1;
                   z <= 18'b000000000000000000;
               end
               
           
   end //always
    

endmodule

------------------------------------------------------------------------
-- Title        Reverse Square-Root (1/sqr(X))                        --
-- File         RSQRT.vhd                                             --
-- Entity       RSQRT                                                 --
-- rev date     coded contents                                        --
-- 001 98/11/05 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity RSQRT is
port(
        X       : in    std_logic_vector(19 downto 0) ; -- Input(20bit)
        ZN      : out   std_logic_vector(3 downto 0) ;  -- Exp(4bit)
        ZM      : out   std_logic_vector(19 downto 0)   -- Man(20bit)
    );
end RSQRT ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of RSQRT is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal  A       : std_logic_vector(9 downto 0) ;        --
constant CONSA  : std_logic_vector(9 downto 0) := "1000000111" ;    -- 2.02734375
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal  B       : std_logic_vector(15 downto 0) ;       -- 
--
-- 3rd stages
-- 26bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXXXX
signal  C       : std_logic_vector(25 downto 0) ;       -- 
--
-- Constant Value
constant CONSX  : std_logic_vector(31 downto 0) := "11000000000000000000000000000000" ; -- 3.0
--
--
-- 0.XXXXXXXX
signal  M       : std_logic_vector(19 downto 0) ;       -- Mantissa
signal  N       : std_logic_vector(3 downto 0) ;        -- Expornent

begin
--------------------------------
-- Reverse Square-Root Argolizm
--
-- X = m x 4^n (m = 0.25~0.999999)
-- Z = 1/sqrt(X) = sqrt(m)/m x 2^-n
--                 ^^^^^^^^^      |
--                  ZM            ZN
-- --1st stage (3.16bit)
-- a = (2.0275551-m)            -- a = 1.78~1.02
-- --2nd stage (5.70bit) : 1000 LCs
-- b1 = (a*a)                   -- b1 = +3.17~+1.04
-- b2 = (m*b1)                  -- b2 = +0.813~+1.0208
-- b3 = (3-b2)/2                -- b3 = +0.99~+1.094
-- b4 = a*b3                    -- b4 = +1.00~+1.98
-- b  = b4
-- --3nd stage (10.82bit) : 2500 LCs
-- c1 = (b*b)                   -- c1 = +3.92~+1.00
-- c2 = (m*c1)                  -- c2 = +0.99~+1.01
-- c3 = (3-c2)/2                -- c3 = +0.99~+1.01
-- c4 = b*c3                    -- c4 = +1.00~+1.99
-- c  = c4
-- --4th stage (21.06bit) : ???? LCs
-- d1 = (c*c)                   -- d1 = +3.98~+1.00
-- d2 = (m*d1)                  -- d2 = +0.99~+1.01
-- d3 = (3-d2)/2                -- d3 = +0.99~+1.01
-- d4 = c*d3                    -- d4 = +1.00~+1.99
-- d  = d4
--
-- ZM = g3
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize                                            --
-----------------------------------------------------------
RSQRT_INIT   : process( X )
    begin
        if( X(19 downto 0) = "00000000000000000000"  ) then
            M <= (others=>'0') ;
            N <= (others=>'0') ;
        else
            -- Generate M,N
            if( X(19 downto 2)     = "000000000000000000" ) then
                M <= X(1 downto 0) & "000000000000000000" ;
                N <= "0001" ;
            elsif( X(19 downto 4)  = "0000000000000000" ) then
                M <= X(3 downto 0) & "0000000000000000" ;
                N <= "0010" ;
            elsif( X(19 downto 6)  = "00000000000000" ) then
                M <= X(5 downto 0) & "00000000000000" ;
                N <= "0011" ;
            elsif( X(19 downto 8)  = "000000000000" ) then
                M <= X(7 downto 0) & "000000000000" ;
                N <= "0100" ;
            elsif( X(19 downto 10) = "0000000000" ) then
                M <= X(9 downto 0) & "0000000000" ;
                N <= "0101" ;
            elsif( X(19 downto 12)  = "00000000" ) then
                M <= X(11 downto 0) & "00000000" ;
                N <= "0110" ;
            elsif( X(19 downto 14)  = "000000" ) then
                M <= X(13 downto 0) & "000000" ;
                N <= "0111" ;
            elsif( X(19 downto 16)  = "0000" ) then
                M <= X(15 downto 0) & "0000" ;
                N <= "1000" ;
            elsif( X(19 downto 18)  = "00" ) then
                M <= X(17 downto 0) & "00" ;
                N <= "1001" ;
            else
                M <= X ;
                N <= "1010" ;
            end if ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 1st stage                                             --
-----------------------------------------------------------
RSQRT_1ST   : process( M )
    begin
        if( M = "00000000000000000000"  ) then
            A <= (others=>'0') ;
        else
            -- A = 2.03-M
            A <= CONSA - ("00" & M(19 downto 12)) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 2nd stage                                             --
-----------------------------------------------------------
RSQRT_1ND   : process( A )
        variable    B1 : std_logic_vector(17 downto 0);  -- A(9bit)*A(9bit)
        variable    B2 : std_logic_vector(16 downto 0);  -- M(8bit)*B1(9bit)
        variable    B3 : std_logic_vector(10 downto 0);  -- 3-B2(11bit)
        variable    B4 : std_logic_vector(19 downto 0);  -- A(9bit)*B3(11bit)
    begin
        if( A = "0000000000"  ) then
            B <= (others=>'0') ;
        else
            B1 := A(8 downto 0) * A(8 downto 0) ;
            B2 := B1(17 downto 9) * M(19 downto 12) ;
            B3 := CONSX(31 downto 21) - B2(16 downto 6) ;
            B4 := B3 * A(8 downto 0) ;
            B <= B4(19 downto 4) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 3rd stage                                             --
-----------------------------------------------------------
RSQRT_3RD   : process( B )
        variable    C1 : std_logic_vector(29 downto 0);  -- B(15bit)*B(15bit)
        variable    C2 : std_logic_vector(31 downto 0);  -- M(16bit)*C1(16bit)
        variable    C3 : std_logic_vector(18 downto 0);  -- 3-C2(19bit)
        variable    C4 : std_logic_vector(33 downto 0);  -- B(15bit)*C3(19bit)
    begin
        if( B = "0000000000000000"  ) then
            C <= (others=>'0') ;
        else
            C1 := B(14 downto 0) * B(14 downto 0) ;
            C2 := C1(29 downto 14) * M(19 downto 4) ;
            C3 := CONSX(31 downto 13) - C2(31 downto 13) ;
            C4 := C3 * B(14 downto 0) ;
            C <= C4(33 downto 8) ;
        end if ;
    end process ;
ZN <= N ;
--ZM <= A & "00000000000" ;
--ZM <= B & "0000" ;
ZM <= C(24 downto 5) ;
end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        Reverse Square-Root (1/sqr(X))                        --
// File         RSQRT.vhd                                             --
// Entity       RSQRT                                                 --
// rev date     coded contents                                        --
// 001 98/11/05 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  rsqrt ( x, zn, zm );
    
    input [19:0]  x ;
    output [3:0]  zn ;
    output [19:0]  zm ;


    reg [17:0] rsqrt_1nd__b1;
    reg [16:0] rsqrt_1nd__b2;
    reg [10:0] rsqrt_1nd__b3;
    reg [19:0] rsqrt_1nd__b4;
    reg [29:0] rsqrt_3rd__c1;
    reg [31:0] rsqrt_3rd__c2;
    reg [18:0] rsqrt_3rd__c3;
    reg [33:0] rsqrt_3rd__c4;
    reg [9:0] a;
    parameter [9:0] consa=10'b1000000111;
    reg [15:0] b;
    reg [25:0] c;
    parameter [31:0] consx=32'b11000000000000000000000000000000;
    reg [19:0] m;
    reg [3:0] n;
    wire [3:0] zn;
    wire [19:0] zm;


    
       
   always @ (x ) begin
           if ((x[19:0] === 20'b00000000000000000000)) 
               begin 
                   m <= {(19-0+1- 0){1'b0}};
                   n <= {(3-0+1- 0){1'b0}};
               end
               
           else 
               begin 
                   if ((x[19:2] === 18'b000000000000000000)) 
                       begin 
                           m <= {x[1:0],18'b000000000000000000};
                           n <= 4'b0001;
                       end
                       
                   else if ((x[19:4] === 16'b0000000000000000)) 
                       begin 
                           m <= {x[3:0],16'b0000000000000000};
                           n <= 4'b0010;
                       end
                       
                   else if ((x[19:6] === 14'b00000000000000)) 
                       begin 
                           m <= {x[5:0],14'b00000000000000};
                           n <= 4'b0011;
                       end
                       
                   else if ((x[19:8] === 12'b000000000000)) 
                       begin 
                           m <= {x[7:0],12'b000000000000};
                           n <= 4'b0100;
                       end
                       
                   else if ((x[19:10] === 10'b0000000000)) 
                       begin 
                           m <= {x[9:0],10'b0000000000};
                           n <= 4'b0101;
                       end
                       
                   else if ((x[19:12] === 8'b00000000)) 
                       begin 
                           m <= {x[11:0],8'b00000000};
                           n <= 4'b0110;
                       end
                       
                   else if ((x[19:14] === 6'b000000)) 
                       begin 
                           m <= {x[13:0],6'b000000};
                           n <= 4'b0111;
                       end
                       
                   else if ((x[19:16] === 4'b0000)) 
                       begin 
                           m <= {x[15:0],4'b0000};
                           n <= 4'b1000;
                       end
                       
                   else if ((x[19:18] === 2'b00)) 
                       begin 
                           m <= {x[17:0],2'b00};
                           n <= 4'b1001;
                       end
                       
                   else 
                       begin 
                           m <= x;
                           n <= 4'b1010;
                       end
                       
                   
                   
               end 
           
   end //always
   
       
   always @ (m ) begin
           if ((m === 20'b00000000000000000000)) 
               a <= {(9-0+1- 0){1'b0}};
               
           else 
               a <= (consa - {2'b00,m[19:12]});
               
           
   end //always
   
       
   always @ (a ) begin
           if ((a === 10'b0000000000)) 
               b <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   rsqrt_1nd__b1 = (a[8:0] * a[8:0]);
                   rsqrt_1nd__b2 = (rsqrt_1nd__b1[17:9] * m[19:12]);
                   rsqrt_1nd__b3 = (consx[31:21] - rsqrt_1nd__b2[16:6]);
                   rsqrt_1nd__b4 = (rsqrt_1nd__b3 * a[8:0]);
                   b <= rsqrt_1nd__b4[19:4];
               end
               
           
   end //always
   
       
   always @ (b ) begin
           if ((b === 16'b0000000000000000)) 
               c <= {(25-0+1- 0){1'b0}};
               
           else 
               begin 
                   rsqrt_3rd__c1 = (b[14:0] * b[14:0]);
                   rsqrt_3rd__c2 = (rsqrt_3rd__c1[29:14] * m[19:4]);
                   rsqrt_3rd__c3 = (consx[31:13] - rsqrt_3rd__c2[31:13]);
                   rsqrt_3rd__c4 = (rsqrt_3rd__c3 * b[14:0]);
                   c <= rsqrt_3rd__c4[33:8];
               end
               
           
   end //always
   
   assign {zn}=n;
   
   assign {zm}=c[24:5];
    

endmodule

------------------------------------------------------------------------
-- Title        Reverse Square-Root (1/sqr(X))                        --
-- File         RSQRT.vhd                                             --
-- Entity       RSQRT                                                 --
-- rev date     coded contents                                        --
-- 001 98/11/05 ueno  Make Original                                   --
-- 002 98/11/10 ueno  4th stage up                                    --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity RSQRT is
port(
        X       : in    std_logic_vector(19 downto 0) ; -- Input(20bit)
        ZN      : out   std_logic_vector(3 downto 0) ;  -- Exp(4bit)
        ZM      : out   std_logic_vector(19 downto 0)   -- Man(20bit)
    );
end RSQRT ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of RSQRT is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal  A       : std_logic_vector(9 downto 0) ;        --
constant CONSA  : std_logic_vector(9 downto 0) := "1000000111" ;    -- 2.02734375
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal  B       : std_logic_vector(15 downto 0) ;       -- 
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  C       : std_logic_vector(23 downto 0) ;       -- 
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  D       : std_logic_vector(23 downto 0) ;       -- 
--
-- Constant Value
constant CONSX  : std_logic_vector(31 downto 0) := "11000000000000000000000000000000" ; -- 3.0
--
--
-- 0.XXXXXXXX
signal  M       : std_logic_vector(19 downto 0) ;       -- Mantissa
signal  N       : std_logic_vector(3 downto 0) ;        -- Expornent

begin
--------------------------------
-- Reverse Square-Root Argolizm
--
-- X = m x 4^n (m = 0.25~0.999999)
-- Z = 1/sqrt(X) = sqrt(m)/m x 2^-n
--                 ^^^^^^^^^      |
--                  ZM            ZN
-- --1st stage (3.16bit)
-- a = (2.0275551-m)            -- a = 1.78~1.02
-- --2nd stage (5.70bit) : 1000 LCs
-- b1 = (a*a)                   -- b1 = +3.17~+1.04
-- b2 = (m*b1)                  -- b2 = +0.813~+1.0208
-- b3 = (3-b2)/2                -- b3 = +0.99~+1.094
-- b4 = a*b3                    -- b4 = +1.00~+1.98
-- b  = b4
-- --3nd stage (10.82bit) : 2500 LCs
-- c1 = (b*b)                   -- c1 = +3.92~+1.00
-- c2 = (m*c1)                  -- c2 = +0.99~+1.01
-- c3 = (3-c2)/2                -- c3 = +0.99~+1.01
-- c4 = b*c3                    -- c4 = +1.00~+1.99
-- c  = c4
-- --4th stage (21.06bit) : 5000 LCs
-- d1 = (c*c)                   -- d1 = +3.98~+1.00
-- d2 = (m*d1)                  -- d2 = +0.99~+1.01
-- d3 = (3-d2)/2                -- d3 = +0.99~+1.01
-- d4 = c*d3                    -- d4 = +1.00~+1.99
-- d  = d4
--
-- ZM = g3
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize                                            --
-----------------------------------------------------------
RSQRT_INIT   : process( X )
    begin
        if( X(19 downto 0) = "00000000000000000000"  ) then
            M <= (others=>'0') ;
            N <= (others=>'0') ;
        else
            -- Generate M,N
            if( X(19 downto 2)     = "000000000000000000" ) then
                M <= X(1 downto 0) & "000000000000000000" ;
                N <= "0001" ;
            elsif( X(19 downto 4)  = "0000000000000000" ) then
                M <= X(3 downto 0) & "0000000000000000" ;
                N <= "0010" ;
            elsif( X(19 downto 6)  = "00000000000000" ) then
                M <= X(5 downto 0) & "00000000000000" ;
                N <= "0011" ;
            elsif( X(19 downto 8)  = "000000000000" ) then
                M <= X(7 downto 0) & "000000000000" ;
                N <= "0100" ;
            elsif( X(19 downto 10) = "0000000000" ) then
                M <= X(9 downto 0) & "0000000000" ;
                N <= "0101" ;
            elsif( X(19 downto 12)  = "00000000" ) then
                M <= X(11 downto 0) & "00000000" ;
                N <= "0110" ;
            elsif( X(19 downto 14)  = "000000" ) then
                M <= X(13 downto 0) & "000000" ;
                N <= "0111" ;
            elsif( X(19 downto 16)  = "0000" ) then
                M <= X(15 downto 0) & "0000" ;
                N <= "1000" ;
            elsif( X(19 downto 18)  = "00" ) then
                M <= X(17 downto 0) & "00" ;
                N <= "1001" ;
            else
                M <= X ;
                N <= "1010" ;
            end if ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 1st stage                                             --
-----------------------------------------------------------
RSQRT_1ST   : process( M )
    begin
        if( M = "00000000000000000000"  ) then
            A <= (others=>'0') ;
        else
            -- A = 2.03-M
            A <= CONSA - ("00" & M(19 downto 12)) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 2nd stage                                             --
-----------------------------------------------------------
RSQRT_1ND   : process( M, A )
        variable    B1 : std_logic_vector(17 downto 0);  -- A(9bit)*A(9bit)
        variable    B2 : std_logic_vector(16 downto 0);  -- M(8bit)*B1(9bit)
        variable    B3 : std_logic_vector(10 downto 0);  -- 3-B2(11bit)
        variable    B4 : std_logic_vector(19 downto 0);  -- A(9bit)*B3(11bit)
    begin
        if( A = "0000000000"  ) then
            B <= (others=>'0') ;
        else
            B1 := A(8 downto 0) * A(8 downto 0) ;
            B2 := B1(17 downto 9) * M(19 downto 12) ;
            B3 := CONSX(31 downto 21) - B2(16 downto 6) ;
            B4 := B3 * A(8 downto 0) ;
            B <= B4(19 downto 4) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 3rd stage                                             --
-----------------------------------------------------------
RSQRT_3RD   : process( M, B )
        variable    C1 : std_logic_vector(29 downto 0);  -- B(15bit)*B(15bit)
        variable    C2 : std_logic_vector(31 downto 0);  -- M(16bit)*C1(16bit)
        variable    C3 : std_logic_vector(18 downto 0);  -- 3-C2(19bit)
        variable    C4 : std_logic_vector(33 downto 0);  -- B(15bit)*C3(19bit)
    begin
        if( B = "0000000000000000"  ) then
            C <= (others=>'0') ;
        else
            C1 := B(14 downto 0) * B(14 downto 0) ;
            C2 := C1(29 downto 14) * M(19 downto 4) ;
            C3 := CONSX(31 downto 13) - C2(31 downto 13) ;
            C4 := C3 * B(14 downto 0) ;
            C <= C4(33 downto 10) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 4th stage                                             --
-----------------------------------------------------------
RSQRT_4TH   : process( M, C )
        variable    D1 : std_logic_vector(39 downto 0);  -- C(20bit)*C(20bit)
        variable    D2 : std_logic_vector(39 downto 0);  -- M(20bit)*D1(20bit)
        variable    D3 : std_logic_vector(23 downto 0);  -- 3-D2(24bit)
        variable    D4 : std_logic_vector(43 downto 0);  -- C(20bit)*D3(24bit)
    begin
        if( C = "000000000000000000000000"  ) then
            D <= (others=>'0') ;
        else
            D1 := C(22 downto 3) * C(22 downto 3) ;
            D2 := D1(39 downto 20) * M(19 downto 0) ;
            D3 := CONSX(31 downto 8) - D2(39 downto 16) ;
            D4 := D3 * C(22 downto 3) ;
            D <= D4(43 downto 20) ;
        end if ;
    end process ;
ZN <= N ;
--ZM <= A & "00000000000" ;
--ZM <= B & "0000" ;
--ZM <= C(22 downto 3) ;
ZM <= D(22 downto 3) ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        Reverse Square-Root (1/sqr(X))                        --
// File         RSQRT.vhd                                             --
// Entity       RSQRT                                                 --
// rev date     coded contents                                        --
// 001 98/11/05 ueno  Make Original                                   --
// 002 98/11/10 ueno  4th stage up                                    --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  rsqrt ( x, zn, zm );
    
    input [19:0]  x ;
    output [3:0]  zn ;
    output [19:0]  zm ;


    reg [17:0] rsqrt_1nd__b1;
    reg [16:0] rsqrt_1nd__b2;
    reg [10:0] rsqrt_1nd__b3;
    reg [19:0] rsqrt_1nd__b4;
    reg [29:0] rsqrt_3rd__c1;
    reg [31:0] rsqrt_3rd__c2;
    reg [18:0] rsqrt_3rd__c3;
    reg [33:0] rsqrt_3rd__c4;
    reg [39:0] rsqrt_4th__d1;
    reg [39:0] rsqrt_4th__d2;
    reg [23:0] rsqrt_4th__d3;
    reg [43:0] rsqrt_4th__d4;
    reg [9:0] a;
    parameter [9:0] consa=10'b1000000111;
    reg [15:0] b;
    reg [23:0] c;
    reg [23:0] d;
    parameter [31:0] consx=32'b11000000000000000000000000000000;
    reg [19:0] m;
    reg [3:0] n;
    wire [3:0] zn;
    wire [19:0] zm;


    
       
   always @ (x ) begin
           if ((x[19:0] === 20'b00000000000000000000)) 
               begin 
                   m <= {(19-0+1- 0){1'b0}};
                   n <= {(3-0+1- 0){1'b0}};
               end
               
           else 
               begin 
                   if ((x[19:2] === 18'b000000000000000000)) 
                       begin 
                           m <= {x[1:0],18'b000000000000000000};
                           n <= 4'b0001;
                       end
                       
                   else if ((x[19:4] === 16'b0000000000000000)) 
                       begin 
                           m <= {x[3:0],16'b0000000000000000};
                           n <= 4'b0010;
                       end
                       
                   else if ((x[19:6] === 14'b00000000000000)) 
                       begin 
                           m <= {x[5:0],14'b00000000000000};
                           n <= 4'b0011;
                       end
                       
                   else if ((x[19:8] === 12'b000000000000)) 
                       begin 
                           m <= {x[7:0],12'b000000000000};
                           n <= 4'b0100;
                       end
                       
                   else if ((x[19:10] === 10'b0000000000)) 
                       begin 
                           m <= {x[9:0],10'b0000000000};
                           n <= 4'b0101;
                       end
                       
                   else if ((x[19:12] === 8'b00000000)) 
                       begin 
                           m <= {x[11:0],8'b00000000};
                           n <= 4'b0110;
                       end
                       
                   else if ((x[19:14] === 6'b000000)) 
                       begin 
                           m <= {x[13:0],6'b000000};
                           n <= 4'b0111;
                       end
                       
                   else if ((x[19:16] === 4'b0000)) 
                       begin 
                           m <= {x[15:0],4'b0000};
                           n <= 4'b1000;
                       end
                       
                   else if ((x[19:18] === 2'b00)) 
                       begin 
                           m <= {x[17:0],2'b00};
                           n <= 4'b1001;
                       end
                       
                   else 
                       begin 
                           m <= x;
                           n <= 4'b1010;
                       end
                       
                   
                   
               end 
           
   end //always
   
       
   always @ (m ) begin
           if ((m === 20'b00000000000000000000)) 
               a <= {(9-0+1- 0){1'b0}};
               
           else 
               a <= (consa - {2'b00,m[19:12]});
               
           
   end //always
   
       
   always @ (m or a ) begin
           if ((a === 10'b0000000000)) 
               b <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   rsqrt_1nd__b1 = (a[8:0] * a[8:0]);
                   rsqrt_1nd__b2 = (rsqrt_1nd__b1[17:9] * m[19:12]);
                   rsqrt_1nd__b3 = (consx[31:21] - rsqrt_1nd__b2[16:6]);
                   rsqrt_1nd__b4 = (rsqrt_1nd__b3 * a[8:0]);
                   b <= rsqrt_1nd__b4[19:4];
               end
               
           
   end //always
   
       
   always @ (m or b ) begin
           if ((b === 16'b0000000000000000)) 
               c <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   rsqrt_3rd__c1 = (b[14:0] * b[14:0]);
                   rsqrt_3rd__c2 = (rsqrt_3rd__c1[29:14] * m[19:4]);
                   rsqrt_3rd__c3 = (consx[31:13] - rsqrt_3rd__c2[31:13]);
                   rsqrt_3rd__c4 = (rsqrt_3rd__c3 * b[14:0]);
                   c <= rsqrt_3rd__c4[33:10];
               end
               
           
   end //always
   
       
   always @ (m or c ) begin
           if ((c === 24'b000000000000000000000000)) 
               d <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   rsqrt_4th__d1 = (c[22:3] * c[22:3]);
                   rsqrt_4th__d2 = (rsqrt_4th__d1[39:20] * m[19:0]);
                   rsqrt_4th__d3 = (consx[31:8] - rsqrt_4th__d2[39:16]);
                   rsqrt_4th__d4 = (rsqrt_4th__d3 * c[22:3]);
                   d <= rsqrt_4th__d4[43:20];
               end
               
           
   end //always
   
   assign {zn}=n;
   
   assign {zm}=d[22:3];
    

endmodule

------------------------------------------------------------------------
-- Title        Reverse X (1/X)                                       --
-- File         REVX.vhd                                              --
-- Entity       REVX                                                  --
-- rev date     coded contents                                        --
-- 001 98/11/10 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity REVX is
port(
        X       : in    std_logic_vector(19 downto 0) ; -- Input(20bit)
        ZN      : out   std_logic_vector(4 downto 0) ;  -- Exp(5bit)
        ZM      : out   std_logic_vector(19 downto 0)   -- Man(20bit)
    );
end REVX ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of REVX is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal  A       : std_logic_vector(9 downto 0) ;        --
constant CONSA  : std_logic_vector(9 downto 0) := "1100000000" ;    -- 3
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal  B       : std_logic_vector(15 downto 0) ;       -- 
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  C       : std_logic_vector(23 downto 0) ;       -- 
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  D       : std_logic_vector(23 downto 0) ;       -- 
--
-- Constant Value
constant CONSX  : std_logic_vector(31 downto 0) := "10000000000000000000000000000000" ; -- 2.0
--
--
-- 0.XXXXXXXX
signal  M       : std_logic_vector(19 downto 0) ;       -- Mantissa
signal  N       : std_logic_vector(4 downto 0) ;        -- Expornent

begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- Z = 1/X = 1/m x 2^-n
--            |      |
--           ZM     ZN
-- --1st stage (3bit)
-- a = (3-2*m)                  -- a = 1~2 (3.00bit)
-- a = (723-482*m)/256          -- a = 1~2 (4.08bit)
-- --2nd stage (6bit) : xxxx LCs
-- b1 = (m*a)                   -- b1 = 1~1.125
-- b2 = (2-b1)                  -- b2 = 0.875~1
-- b3 = a*b2                    -- b3 = 1~2
-- b  = b3
-- --3nd stage (12bit) : xxxx LCs
-- c1 = (m*b)                   -- c1 = 0.98~1
-- c2 = (2-c1)                  -- c2 = 1~1.01
-- c3 = b*c2                    -- c3 = 1~2
-- c  = c4
-- --4th stage (24bit) : ???? LCs
-- d1 = (m*c)                   -- d1 = 0.99~1
-- d2 = (3-d1)                  -- d2 = 1~1.00
-- d3 = c*d2                    -- d3 = 1~2
-- d  = d4
--
-- ZM = d
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize                                            --
-----------------------------------------------------------
REVX_INIT   : process( X )
    begin
        if( X(19 downto 0) = "00000000000000000000"  ) then
            M <= (others=>'0') ;
            N <= (others=>'0') ;
        else
            -- Generate M,N
            if( X(19 downto 1)     = "0000000000000000000" ) then
                M <=          X(0) & "0000000000000000000" ;
                N <= "00001" ;
            elsif( X(19 downto 2)  = "000000000000000000" ) then
                M <= X(1 downto 0) & "000000000000000000" ;
                N <= "00010" ;
            elsif( X(19 downto 3)  = "00000000000000000" ) then
                M <= X(2 downto 0) & "00000000000000000" ;
                N <= "00011" ;
            elsif( X(19 downto 4)  = "0000000000000000" ) then
                M <= X(3 downto 0) & "0000000000000000" ;
                N <= "00100" ;
            elsif( X(19 downto 5)  = "000000000000000" ) then
                M <= X(4 downto 0) & "000000000000000" ;
                N <= "00101" ;
            elsif( X(19 downto 6)  = "00000000000000" ) then
                M <= X(5 downto 0) & "00000000000000" ;
                N <= "00110" ;
            elsif( X(19 downto 7)  = "0000000000000" ) then
                M <= X(6 downto 0) & "0000000000000" ;
                N <= "00111" ;
            elsif( X(19 downto 8)  = "000000000000" ) then
                M <= X(7 downto 0) & "000000000000" ;
                N <= "01000" ;
            elsif( X(19 downto 9)  = "00000000000" ) then
                M <= X(8 downto 0) & "00000000000" ;
                N <= "01001" ;
            elsif( X(19 downto 10) = "0000000000" ) then
                M <= X(9 downto 0) & "0000000000" ;
                N <= "01010" ;
            elsif( X(19 downto 11)  = "000000000" ) then
                M <= X(10 downto 0) & "000000000" ;
                N <= "01011" ;
            elsif( X(19 downto 12)  = "00000000" ) then
                M <= X(11 downto 0) & "00000000" ;
                N <= "01100" ;
            elsif( X(19 downto 13)  = "0000000" ) then
                M <= X(12 downto 0) & "0000000" ;
                N <= "01101" ;
            elsif( X(19 downto 14)  = "000000" ) then
                M <= X(13 downto 0) & "000000" ;
                N <= "01110" ;
            elsif( X(19 downto 15)  = "00000" ) then
                M <= X(14 downto 0) & "00000" ;
                N <= "01111" ;
            elsif( X(19 downto 16)  = "0000" ) then
                M <= X(15 downto 0) & "0000" ;
                N <= "10000" ;
            elsif( X(19 downto 17)  = "000" ) then
                M <= X(16 downto 0) & "000" ;
                N <= "10001" ;
            elsif( X(19 downto 18)  = "00" ) then
                M <= X(17 downto 0) & "00" ;
                N <= "10010" ;
            elsif(            X(19) = '0' ) then
                M <= X(18 downto 0) & '0' ;
                N <= "10011" ;
            else
                M <= X ;
                N <= "10100" ;
            end if ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 1st stage                                             --
-----------------------------------------------------------
REVX_1ST   : process( M )
    begin
        if( M = "00000000000000000000"  ) then
            A <= (others=>'0') ;
        else
            -- A = 3-2*M
            A <= CONSA - ('0' & M(19 downto 11)) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 2nd stage                                             --
-----------------------------------------------------------
REVX_1ND   : process( M, A )
        variable    B1 : std_logic_vector(19 downto 0);  -- M(10bit)*A(10bit)   XX.XX....
        variable    B2 : std_logic_vector(11 downto 0);  -- 2-B1(12bit)          X.XX....
        variable    B3 : std_logic_vector(21 downto 0);  -- A(10bit)*B2(12bit) XXX.XX....
    begin
        if( A = "0000000000"  ) then
            B <= (others=>'0') ;
        else
            B1 := M(19 downto 10) * A ;
            B2 := CONSX(30 downto 19) - B1(18 downto 7) ;
            B3 := B2 * A ;
            B <= B3(20 downto 5) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 3rd stage                                             --
-----------------------------------------------------------
REVX_3RD   : process( M, B )
        variable    C1 : std_logic_vector(31 downto 0);  -- M(16bit)*B(16bit)   XX.XX...
        variable    C2 : std_logic_vector(19 downto 0);  -- 2-C1(20bit)          X.XX...
        variable    C3 : std_logic_vector(35 downto 0);  -- B(16bit)*C2(20bit) XXX.XX...
    begin
        if( B = "0000000000000000"  ) then
            C <= (others=>'0') ;
        else
            C1 := B * M(19 downto 4) ;
            C2 := CONSX(30 downto 11) - C1(30 downto 11) ;
            C3 := C2 * B ;
            C <= C3(34 downto 11) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 4th stage                                             --
-----------------------------------------------------------
REVX_4TH   : process( M, C )
        variable    D1 : std_logic_vector(39 downto 0);  -- M(20bit)*C(20bit)   XX.XX...
        variable    D2 : std_logic_vector(23 downto 0);  -- 2-D1(24bit)          X.XX...
        variable    D3 : std_logic_vector(43 downto 0);  -- C(20bit)*D2(24bit) XXX.XX...
    begin
        if( C = "000000000000000000000000"  ) then
            D <= (others=>'0') ;
        else
            D1 := C(23 downto 4) * M ;
            D2 := CONSX(30 downto 7) - D1(38 downto 15) ;
            D3 := D2 * C(23 downto 4) ;
            D <= D3(42 downto 19) ;
        end if ;
    end process ;
ZN <= N ;
--ZM <= A & "0000000000" ;
--ZM <= B & "0000" ;
ZM <= C(23 downto 4) ;
--ZM <= D(23 downto 4) ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        Reverse X (1/X)                                       --
// File         REVX.vhd                                              --
// Entity       REVX                                                  --
// rev date     coded contents                                        --
// 001 98/11/10 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  revx ( x, zn, zm );
    
    input [19:0]  x ;
    output [4:0]  zn ;
    output [19:0]  zm ;


    reg [19:0] revx_1nd__b1;
    reg [11:0] revx_1nd__b2;
    reg [21:0] revx_1nd__b3;
    reg [31:0] revx_3rd__c1;
    reg [19:0] revx_3rd__c2;
    reg [35:0] revx_3rd__c3;
    reg [39:0] revx_4th__d1;
    reg [23:0] revx_4th__d2;
    reg [43:0] revx_4th__d3;
    reg [9:0] a;
    parameter [9:0] consa=10'b1100000000;
    reg [15:0] b;
    reg [23:0] c;
    reg [23:0] d;
    parameter [31:0] consx=32'b10000000000000000000000000000000;
    reg [19:0] m;
    reg [4:0] n;
    wire [4:0] zn;
    wire [19:0] zm;


    
       
   always @ (x ) begin
           if ((x[19:0] === 20'b00000000000000000000)) 
               begin 
                   m <= {(19-0+1- 0){1'b0}};
                   n <= {(4-0+1- 0){1'b0}};
               end
               
           else 
               begin 
                   if ((x[19:1] === 19'b0000000000000000000)) 
                       begin 
                           m <= {x[0],19'b0000000000000000000};
                           n <= 5'b00001;
                       end
                       
                   else if ((x[19:2] === 18'b000000000000000000)) 
                       begin 
                           m <= {x[1:0],18'b000000000000000000};
                           n <= 5'b00010;
                       end
                       
                   else if ((x[19:3] === 17'b00000000000000000)) 
                       begin 
                           m <= {x[2:0],17'b00000000000000000};
                           n <= 5'b00011;
                       end
                       
                   else if ((x[19:4] === 16'b0000000000000000)) 
                       begin 
                           m <= {x[3:0],16'b0000000000000000};
                           n <= 5'b00100;
                       end
                       
                   else if ((x[19:5] === 15'b000000000000000)) 
                       begin 
                           m <= {x[4:0],15'b000000000000000};
                           n <= 5'b00101;
                       end
                       
                   else if ((x[19:6] === 14'b00000000000000)) 
                       begin 
                           m <= {x[5:0],14'b00000000000000};
                           n <= 5'b00110;
                       end
                       
                   else if ((x[19:7] === 13'b0000000000000)) 
                       begin 
                           m <= {x[6:0],13'b0000000000000};
                           n <= 5'b00111;
                       end
                       
                   else if ((x[19:8] === 12'b000000000000)) 
                       begin 
                           m <= {x[7:0],12'b000000000000};
                           n <= 5'b01000;
                       end
                       
                   else if ((x[19:9] === 11'b00000000000)) 
                       begin 
                           m <= {x[8:0],11'b00000000000};
                           n <= 5'b01001;
                       end
                       
                   else if ((x[19:10] === 10'b0000000000)) 
                       begin 
                           m <= {x[9:0],10'b0000000000};
                           n <= 5'b01010;
                       end
                       
                   else if ((x[19:11] === 9'b000000000)) 
                       begin 
                           m <= {x[10:0],9'b000000000};
                           n <= 5'b01011;
                       end
                       
                   else if ((x[19:12] === 8'b00000000)) 
                       begin 
                           m <= {x[11:0],8'b00000000};
                           n <= 5'b01100;
                       end
                       
                   else if ((x[19:13] === 7'b0000000)) 
                       begin 
                           m <= {x[12:0],7'b0000000};
                           n <= 5'b01101;
                       end
                       
                   else if ((x[19:14] === 6'b000000)) 
                       begin 
                           m <= {x[13:0],6'b000000};
                           n <= 5'b01110;
                       end
                       
                   else if ((x[19:15] === 5'b00000)) 
                       begin 
                           m <= {x[14:0],5'b00000};
                           n <= 5'b01111;
                       end
                       
                   else if ((x[19:16] === 4'b0000)) 
                       begin 
                           m <= {x[15:0],4'b0000};
                           n <= 5'b10000;
                       end
                       
                   else if ((x[19:17] === 3'b000)) 
                       begin 
                           m <= {x[16:0],3'b000};
                           n <= 5'b10001;
                       end
                       
                   else if ((x[19:18] === 2'b00)) 
                       begin 
                           m <= {x[17:0],2'b00};
                           n <= 5'b10010;
                       end
                       
                   else if ((x[19] === 1'b0)) 
                       begin 
                           m <= {x[18:0],1'b0};
                           n <= 5'b10011;
                       end
                       
                   else 
                       begin 
                           m <= x;
                           n <= 5'b10100;
                       end
                       
                   
                   
               end 
           
   end //always
   
       
   always @ (m ) begin
           if ((m === 20'b00000000000000000000)) 
               a <= {(9-0+1- 0){1'b0}};
               
           else 
               a <= (consa - {1'b0,m[19:11]});
               
           
   end //always
   
       
   always @ (m or a ) begin
           if ((a === 10'b0000000000)) 
               b <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_1nd__b1 = (m[19:10] * a);
                   revx_1nd__b2 = (consx[30:19] - revx_1nd__b1[18:7]);
                   revx_1nd__b3 = (revx_1nd__b2 * a);
                   b <= revx_1nd__b3[20:5];
               end
               
           
   end //always
   
       
   always @ (m or b ) begin
           if ((b === 16'b0000000000000000)) 
               c <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_3rd__c1 = (b * m[19:4]);
                   revx_3rd__c2 = (consx[30:11] - revx_3rd__c1[30:11]);
                   revx_3rd__c3 = (revx_3rd__c2 * b);
                   c <= revx_3rd__c3[34:11];
               end
               
           
   end //always
   
       
   always @ (m or c ) begin
           if ((c === 24'b000000000000000000000000)) 
               d <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_4th__d1 = (c[23:4] * m);
                   revx_4th__d2 = (consx[30:7] - revx_4th__d1[38:15]);
                   revx_4th__d3 = (revx_4th__d2 * c[23:4]);
                   d <= revx_4th__d3[42:19];
               end
               
           
   end //always
   
   assign {zn}=n;
   
   assign {zm}=c[23:4];
    

endmodule

------------------------------------------------------------------------
-- Title        Reverse X (1/X)                                       --
-- File         REVX.vhd                                              --
-- Entity       REVX                                                  --
-- rev date     coded contents                                        --
-- 001 98/11/10 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity REVX is
port(
        X       : in    std_logic_vector(19 downto 0) ; -- Input(20bit)
        ZN      : out   std_logic_vector(4 downto 0) ;  -- Exp(5bit)
        ZM      : out   std_logic_vector(19 downto 0)   -- Man(20bit)
    );
end REVX ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of REVX is
--
-- 1st stages
-- 10bit calc
-- XX.XXXXXXXX
signal  A       : std_logic_vector(9 downto 0) ;        --
constant CONSA  : std_logic_vector(9 downto 0) := "1100000000" ;    -- 3
--
-- 2nd stages
-- 16bit calc
-- XX.XXXXXXXXXXXXXXXX
signal  B       : std_logic_vector(15 downto 0) ;       -- 
--
-- 3rd stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  C       : std_logic_vector(23 downto 0) ;       -- 
--
-- 4th stages
-- 24bit calc
-- XX.XXXXXXXXXXXXXXXXXXXXXX
signal  D       : std_logic_vector(23 downto 0) ;       -- 
--
-- Constant Value
constant CONSX  : std_logic_vector(31 downto 0) := "10000000000000000000000000000000" ; -- 2.0
--
--
-- 0.XXXXXXXX
signal  M       : std_logic_vector(19 downto 0) ;       -- Mantissa
signal  N       : std_logic_vector(4 downto 0) ;        -- Expornent

begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- Z = 1/X = 1/m x 2^-n
--            |      |
--           ZM     ZN
-- --1st stage (3bit)
-- a = (3-2*m)                  -- a = 1~2 (3.00bit)
-- a = (723-482*m)/256          -- a = 1~2 (4.08bit)
-- --2nd stage (6bit) : xxxx LCs
-- b1 = (m*a)                   -- b1 = 1~1.125
-- b2 = (2-b1)                  -- b2 = 0.875~1
-- b3 = a*b2                    -- b3 = 1~2
-- b  = b3
-- --3nd stage (12bit) : xxxx LCs
-- c1 = (m*b)                   -- c1 = 0.98~1
-- c2 = (2-c1)                  -- c2 = 1~1.01
-- c3 = b*c2                    -- c3 = 1~2
-- c  = c4
-- --4th stage (24bit) : ???? LCs
-- d1 = (m*c)                   -- d1 = 0.99~1
-- d2 = (3-d1)                  -- d2 = 1~1.00
-- d3 = c*d2                    -- d3 = 1~2
-- d  = d4
--
-- ZM = d
-- ZN = n
--------------------------------
-----------------------------------------------------------
-- Initialize                                            --
-----------------------------------------------------------
REVX_INIT   : process( X )
    begin
        if( X(19 downto 0) = "00000000000000000000"  ) then
            M <= (others=>'0') ;
            N <= (others=>'0') ;
        else
            -- Generate M,N
            if( X(19 downto 1)     = "0000000000000000000" ) then
                M <=          X(0) & "0000000000000000000" ;
                N <= "00001" ;
            elsif( X(19 downto 2)  = "000000000000000000" ) then
                M <= X(1 downto 0) & "000000000000000000" ;
                N <= "00010" ;
            elsif( X(19 downto 3)  = "00000000000000000" ) then
                M <= X(2 downto 0) & "00000000000000000" ;
                N <= "00011" ;
            elsif( X(19 downto 4)  = "0000000000000000" ) then
                M <= X(3 downto 0) & "0000000000000000" ;
                N <= "00100" ;
            elsif( X(19 downto 5)  = "000000000000000" ) then
                M <= X(4 downto 0) & "000000000000000" ;
                N <= "00101" ;
            elsif( X(19 downto 6)  = "00000000000000" ) then
                M <= X(5 downto 0) & "00000000000000" ;
                N <= "00110" ;
            elsif( X(19 downto 7)  = "0000000000000" ) then
                M <= X(6 downto 0) & "0000000000000" ;
                N <= "00111" ;
            elsif( X(19 downto 8)  = "000000000000" ) then
                M <= X(7 downto 0) & "000000000000" ;
                N <= "01000" ;
            elsif( X(19 downto 9)  = "00000000000" ) then
                M <= X(8 downto 0) & "00000000000" ;
                N <= "01001" ;
            elsif( X(19 downto 10) = "0000000000" ) then
                M <= X(9 downto 0) & "0000000000" ;
                N <= "01010" ;
            elsif( X(19 downto 11)  = "000000000" ) then
                M <= X(10 downto 0) & "000000000" ;
                N <= "01011" ;
            elsif( X(19 downto 12)  = "00000000" ) then
                M <= X(11 downto 0) & "00000000" ;
                N <= "01100" ;
            elsif( X(19 downto 13)  = "0000000" ) then
                M <= X(12 downto 0) & "0000000" ;
                N <= "01101" ;
            elsif( X(19 downto 14)  = "000000" ) then
                M <= X(13 downto 0) & "000000" ;
                N <= "01110" ;
            elsif( X(19 downto 15)  = "00000" ) then
                M <= X(14 downto 0) & "00000" ;
                N <= "01111" ;
            elsif( X(19 downto 16)  = "0000" ) then
                M <= X(15 downto 0) & "0000" ;
                N <= "10000" ;
            elsif( X(19 downto 17)  = "000" ) then
                M <= X(16 downto 0) & "000" ;
                N <= "10001" ;
            elsif( X(19 downto 18)  = "00" ) then
                M <= X(17 downto 0) & "00" ;
                N <= "10010" ;
            elsif(            X(19) = '0' ) then
                M <= X(18 downto 0) & '0' ;
                N <= "10011" ;
            else
                M <= X ;
                N <= "10100" ;
            end if ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 1st stage                                             --
-----------------------------------------------------------
REVX_1ST   : process( M )
    begin
        if( M = "00000000000000000000"  ) then
            A <= (others=>'0') ;
        else
            -- A = 3-2*M
            A <= CONSA - ('0' & M(19 downto 11)) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 2nd stage                                             --
-----------------------------------------------------------
REVX_1ND   : process( M, A )
        variable    B1 : std_logic_vector(19 downto 0);  -- M(10bit)*A(10bit)   XX.XX....
        variable    B2 : std_logic_vector(11 downto 0);  -- 2-B1(12bit)          X.XX....
        variable    B3 : std_logic_vector(21 downto 0);  -- A(10bit)*B2(12bit) XXX.XX....
    begin
        if( A = "0000000000"  ) then
            B <= (others=>'0') ;
        else
            B1 := M(19 downto 10) * A ;
            B2 := CONSX(30 downto 19) - B1(18 downto 7) ;
            B3 := B2 * A ;
            B <= B3(20 downto 5) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 3rd stage                                             --
-----------------------------------------------------------
REVX_3RD   : process( M, B )
        variable    C1 : std_logic_vector(31 downto 0);  -- M(16bit)*B(16bit)   XX.XX...
        variable    C2 : std_logic_vector(19 downto 0);  -- 2-C1(20bit)          X.XX...
        variable    C3 : std_logic_vector(35 downto 0);  -- B(16bit)*C2(20bit) XXX.XX...
    begin
        if( B = "0000000000000000"  ) then
            C <= (others=>'0') ;
        else
            C1 := B * M(19 downto 4) ;
            C2 := CONSX(30 downto 11) - C1(30 downto 11) ;
            C3 := C2 * B ;
            C <= C3(34 downto 11) ;
        end if ;
    end process ;
-----------------------------------------------------------
-- 4th stage                                             --
-----------------------------------------------------------
REVX_4TH   : process( M, C )
        variable    D1 : std_logic_vector(39 downto 0);  -- M(20bit)*C(20bit)   XX.XX...
        variable    D2 : std_logic_vector(23 downto 0);  -- 2-D1(24bit)          X.XX...
        variable    D3 : std_logic_vector(43 downto 0);  -- C(20bit)*D2(24bit) XXX.XX...
    begin
        if( C = "000000000000000000000000"  ) then
            D <= (others=>'0') ;
        else
            D1 := C(23 downto 4) * M ;
            D2 := CONSX(30 downto 7) - D1(38 downto 15) ;
            D3 := D2 * C(23 downto 4) ;
            D <= D3(42 downto 19) ;
        end if ;
    end process ;
ZN <= N ;
--ZM <= A & "0000000000" ;
--ZM <= B & "0000" ;
--ZM <= C(23 downto 4) ;
ZM <= D(23 downto 4) ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        Reverse X (1/X)                                       --
// File         REVX.vhd                                              --
// Entity       REVX                                                  --
// rev date     coded contents                                        --
// 001 98/11/10 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  revx ( x, zn, zm );
    
    input [19:0]  x ;
    output [4:0]  zn ;
    output [19:0]  zm ;


    reg [19:0] revx_1nd__b1;
    reg [11:0] revx_1nd__b2;
    reg [21:0] revx_1nd__b3;
    reg [31:0] revx_3rd__c1;
    reg [19:0] revx_3rd__c2;
    reg [35:0] revx_3rd__c3;
    reg [39:0] revx_4th__d1;
    reg [23:0] revx_4th__d2;
    reg [43:0] revx_4th__d3;
    reg [9:0] a;
    parameter [9:0] consa=10'b1100000000;
    reg [15:0] b;
    reg [23:0] c;
    reg [23:0] d;
    parameter [31:0] consx=32'b10000000000000000000000000000000;
    reg [19:0] m;
    reg [4:0] n;
    wire [4:0] zn;
    wire [19:0] zm;


    
       
   always @ (x ) begin
           if ((x[19:0] === 20'b00000000000000000000)) 
               begin 
                   m <= {(19-0+1- 0){1'b0}};
                   n <= {(4-0+1- 0){1'b0}};
               end
               
           else 
               begin 
                   if ((x[19:1] === 19'b0000000000000000000)) 
                       begin 
                           m <= {x[0],19'b0000000000000000000};
                           n <= 5'b00001;
                       end
                       
                   else if ((x[19:2] === 18'b000000000000000000)) 
                       begin 
                           m <= {x[1:0],18'b000000000000000000};
                           n <= 5'b00010;
                       end
                       
                   else if ((x[19:3] === 17'b00000000000000000)) 
                       begin 
                           m <= {x[2:0],17'b00000000000000000};
                           n <= 5'b00011;
                       end
                       
                   else if ((x[19:4] === 16'b0000000000000000)) 
                       begin 
                           m <= {x[3:0],16'b0000000000000000};
                           n <= 5'b00100;
                       end
                       
                   else if ((x[19:5] === 15'b000000000000000)) 
                       begin 
                           m <= {x[4:0],15'b000000000000000};
                           n <= 5'b00101;
                       end
                       
                   else if ((x[19:6] === 14'b00000000000000)) 
                       begin 
                           m <= {x[5:0],14'b00000000000000};
                           n <= 5'b00110;
                       end
                       
                   else if ((x[19:7] === 13'b0000000000000)) 
                       begin 
                           m <= {x[6:0],13'b0000000000000};
                           n <= 5'b00111;
                       end
                       
                   else if ((x[19:8] === 12'b000000000000)) 
                       begin 
                           m <= {x[7:0],12'b000000000000};
                           n <= 5'b01000;
                       end
                       
                   else if ((x[19:9] === 11'b00000000000)) 
                       begin 
                           m <= {x[8:0],11'b00000000000};
                           n <= 5'b01001;
                       end
                       
                   else if ((x[19:10] === 10'b0000000000)) 
                       begin 
                           m <= {x[9:0],10'b0000000000};
                           n <= 5'b01010;
                       end
                       
                   else if ((x[19:11] === 9'b000000000)) 
                       begin 
                           m <= {x[10:0],9'b000000000};
                           n <= 5'b01011;
                       end
                       
                   else if ((x[19:12] === 8'b00000000)) 
                       begin 
                           m <= {x[11:0],8'b00000000};
                           n <= 5'b01100;
                       end
                       
                   else if ((x[19:13] === 7'b0000000)) 
                       begin 
                           m <= {x[12:0],7'b0000000};
                           n <= 5'b01101;
                       end
                       
                   else if ((x[19:14] === 6'b000000)) 
                       begin 
                           m <= {x[13:0],6'b000000};
                           n <= 5'b01110;
                       end
                       
                   else if ((x[19:15] === 5'b00000)) 
                       begin 
                           m <= {x[14:0],5'b00000};
                           n <= 5'b01111;
                       end
                       
                   else if ((x[19:16] === 4'b0000)) 
                       begin 
                           m <= {x[15:0],4'b0000};
                           n <= 5'b10000;
                       end
                       
                   else if ((x[19:17] === 3'b000)) 
                       begin 
                           m <= {x[16:0],3'b000};
                           n <= 5'b10001;
                       end
                       
                   else if ((x[19:18] === 2'b00)) 
                       begin 
                           m <= {x[17:0],2'b00};
                           n <= 5'b10010;
                       end
                       
                   else if ((x[19] === 1'b0)) 
                       begin 
                           m <= {x[18:0],1'b0};
                           n <= 5'b10011;
                       end
                       
                   else 
                       begin 
                           m <= x;
                           n <= 5'b10100;
                       end
                       
                   
                   
               end 
           
   end //always
   
       
   always @ (m ) begin
           if ((m === 20'b00000000000000000000)) 
               a <= {(9-0+1- 0){1'b0}};
               
           else 
               a <= (consa - {1'b0,m[19:11]});
               
           
   end //always
   
       
   always @ (m or a ) begin
           if ((a === 10'b0000000000)) 
               b <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_1nd__b1 = (m[19:10] * a);
                   revx_1nd__b2 = (consx[30:19] - revx_1nd__b1[18:7]);
                   revx_1nd__b3 = (revx_1nd__b2 * a);
                   b <= revx_1nd__b3[20:5];
               end
               
           
   end //always
   
       
   always @ (m or b ) begin
           if ((b === 16'b0000000000000000)) 
               c <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_3rd__c1 = (b * m[19:4]);
                   revx_3rd__c2 = (consx[30:11] - revx_3rd__c1[30:11]);
                   revx_3rd__c3 = (revx_3rd__c2 * b);
                   c <= revx_3rd__c3[34:11];
               end
               
           
   end //always
   
       
   always @ (m or c ) begin
           if ((c === 24'b000000000000000000000000)) 
               d <= {(23-0+1- 0){1'b0}};
               
           else 
               begin 
                   revx_4th__d1 = (c[23:4] * m);
                   revx_4th__d2 = (consx[30:7] - revx_4th__d1[38:15]);
                   revx_4th__d3 = (revx_4th__d2 * c[23:4]);
                   d <= revx_4th__d3[42:19];
               end
               
           
   end //always
   
   assign {zn}=n;
   
   assign {zm}=d[23:4];
    

endmodule

------------------------------------------------------------------------
-- Title        Logalizm X (log(X))                                   --
-- File         LOG.vhd                                               --
-- Entity       LOG                                                   --
-- rev date     coded contents                                        --
-- 001 98/11/17 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity LOG is
port(
-- XXXXXXXXXXXXXXXXXXXX.    Integer Value
        X       : in    std_logic_vector(19 downto 0) ; -- Input(20bit)
-- XXXX.XXXXXXXXXXXXXXXX    Fixed Point Value
        Z       : out   std_logic_vector(19 downto 0)   -- Output(20bit)
    );
end LOG ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of LOG is
-- log(2)
-- .XXXXXXXXXXXXXXXX
constant LOG2V  : std_logic_vector(15 downto 0) := "1011000101110010" ;
-- 1/2 = shift1
-- 1/3
constant CONS3  : std_logic_vector(15 downto 0) := "0101010101010101" ; -- 4bit
-- 1/4 = shift2
-- 1/5
-- 1/6 = 1/3&shift
-- 1/7
constant CONS5  : std_logic_vector(15 downto 0) := "0011001100110011" ; -- 7bit
constant CONS7  : std_logic_vector(15 downto 0) := "0010010010010010" ; -- 9bit
-- 1/8 = shift3
-- 1/9
-- 1/10 = 1/5&shift
-- 1/11
-- 1/12 = 1/3&shift2
-- 1/13
-- 1/14 = 1/7&shift2
-- 1/15
constant CONS9  : std_logic_vector(15 downto 0) := "0001110001110001" ; -- 11bit
constant CONS11 : std_logic_vector(15 downto 0) := "0001011101000101" ; -- 14bit
constant CONS13 : std_logic_vector(15 downto 0) := "0001001110110001" ; -- 16bit
constant CONS15 : std_logic_vector(15 downto 0) := "0001000100010001" ; -- 18bit
--
-- .XXXXXXXXXXXXXXXX
signal  Y       : std_logic_vector(15 downto 0) ;       -- Log( M )
--
signal  F       : std_logic_vector(20 downto 0) ;       -- N*log(2)
signal  G       : std_logic_vector(20 downto 0) ;       -- temp Z
--
-- 0.XXXXXXXX
signal  M       : std_logic_vector(19 downto 0) ;       -- Mantissa
signal  N       : std_logic_vector(4 downto 0) ;        -- Expornent

begin
--------------------------------
-- Reverse X Argolizm (X>0)
--
-- X = m x 2^n (m = 0.5~0.999999)
-- m = 1-h
-- Z = log(2)*n+log(m)
--     log(2)*n-(h+h^2/2+h^3/3+h^4/4+ ....)
--
--------------------------------
-----------------------------------------------------------
-- Initialize                                            --
-----------------------------------------------------------
FLOT_INIT   : process( X )
    begin
        if( X(19 downto 0) = "00000000000000000000"  ) then
            M <= (others=>'0') ;
            N <= (others=>'0') ;
        else
            -- Generate M,N
            if( X(19 downto 1)     = "0000000000000000000" ) then
                M <=          X(0) & "0000000000000000000" ;
                N <= "00001" ;
            elsif( X(19 downto 2)  = "000000000000000000" ) then
                M <= X(1 downto 0) & "000000000000000000" ;
                N <= "00010" ;
            elsif( X(19 downto 3)  = "00000000000000000" ) then
                M <= X(2 downto 0) & "00000000000000000" ;
                N <= "00011" ;
            elsif( X(19 downto 4)  = "0000000000000000" ) then
                M <= X(3 downto 0) & "0000000000000000" ;
                N <= "00100" ;
            elsif( X(19 downto 5)  = "000000000000000" ) then
                M <= X(4 downto 0) & "000000000000000" ;
                N <= "00101" ;
            elsif( X(19 downto 6)  = "00000000000000" ) then
                M <= X(5 downto 0) & "00000000000000" ;
                N <= "00110" ;
            elsif( X(19 downto 7)  = "0000000000000" ) then
                M <= X(6 downto 0) & "0000000000000" ;
                N <= "00111" ;
            elsif( X(19 downto 8)  = "000000000000" ) then
                M <= X(7 downto 0) & "000000000000" ;
                N <= "01000" ;
            elsif( X(19 downto 9)  = "00000000000" ) then
                M <= X(8 downto 0) & "00000000000" ;
                N <= "01001" ;
            elsif( X(19 downto 10) = "0000000000" ) then
                M <= X(9 downto 0) & "0000000000" ;
                N <= "01010" ;
            elsif( X(19 downto 11)  = "000000000" ) then
                M <= X(10 downto 0) & "000000000" ;
                N <= "01011" ;
            elsif( X(19 downto 12)  = "00000000" ) then
                M <= X(11 downto 0) & "00000000" ;
                N <= "01100" ;
            elsif( X(19 downto 13)  = "0000000" ) then
                M <= X(12 downto 0) & "0000000" ;
                N <= "01101" ;
            elsif( X(19 downto 14)  = "000000" ) then
                M <= X(13 downto 0) & "000000" ;
                N <= "01110" ;
            elsif( X(19 downto 15)  = "00000" ) then
                M <= X(14 downto 0) & "00000" ;
                N <= "01111" ;
            elsif( X(19 downto 16)  = "0000" ) then
                M <= X(15 downto 0) & "0000" ;
                N <= "10000" ;
            elsif( X(19 downto 17)  = "000" ) then
                M <= X(16 downto 0) & "000" ;
                N <= "10001" ;
            elsif( X(19 downto 18)  = "00" ) then
                M <= X(17 downto 0) & "00" ;
                N <= "10010" ;
            elsif(            X(19) = '0' ) then
                M <= X(18 downto 0) & '0' ;
                N <= "10011" ;
            else
                M <= X ;
                N <= "10100" ;
            end if ;
        end if ;
    end process ;
-----------------------------------------------------------
-- logalizm calculate                                    --
-----------------------------------------------------------
LOG_CONV    : process( M )
        variable    TMP : std_logic_vector(19 downto 0);  -- 1-m
        variable    H   : std_logic_vector(15 downto 0);  -- 1-m
        variable    B1  : std_logic_vector(15 downto 0);  -- H
        variable    B2  : std_logic_vector(31 downto 0);  -- H^2
        variable    B3  : std_logic_vector(31 downto 0);  -- H^3
        variable    B4  : std_logic_vector(31 downto 0);  -- H^4
        variable    B5  : std_logic_vector(31 downto 0);  -- 
        variable    B6  : std_logic_vector(31 downto 0);  -- 
        variable    B7  : std_logic_vector(31 downto 0);  -- 
        variable    B8  : std_logic_vector(31 downto 0);  -- 
        variable    B9  : std_logic_vector(31 downto 0);  -- 
        variable    B10 : std_logic_vector(31 downto 0);  -- 
        variable    B11 : std_logic_vector(31 downto 0);  -- 
        variable    B12 : std_logic_vector(31 downto 0);  -- 
        variable    B13 : std_logic_vector(31 downto 0);  -- 
        variable    C1  : std_logic_vector(15 downto 0);  -- H
        variable    C2  : std_logic_vector(15 downto 0);  -- H^2
        variable    C3  : std_logic_vector(15 downto 0);  -- H^3
        variable    C4  : std_logic_vector(15 downto 0);  -- H^4
        variable    C5  : std_logic_vector(15 downto 0);  -- 
        variable    C6  : std_logic_vector(15 downto 0);  -- 
        variable    C7  : std_logic_vector(15 downto 0);  -- 
        variable    C8  : std_logic_vector(15 downto 0);  -- 
        variable    C9  : std_logic_vector(15 downto 0);  -- 
        variable    C10 : std_logic_vector(15 downto 0);  -- 
        variable    C11 : std_logic_vector(15 downto 0);  -- 
        variable    C12 : std_logic_vector(15 downto 0);  -- 
        variable    C13 : std_logic_vector(15 downto 0);  -- 
        variable    D   : std_logic_vector(15 downto 0);  -- 
    begin
        if( M = "00000000000000000000"  ) then
            Y <= (others=>'0') ;
        else
            -- TMP = -M
            TMP := "00000000000000000000" - M ;
            H := TMP(19 downto 4) ;
            -- BEKI
            B1  := H ;
            B2  := H*H ;
            B3  := B2(31 downto 16)*H ;
            B4  := B2(31 downto 16)*B2(31 downto 16) ;
            B5  := B4(31 downto 16)*H ;
            B6  := B4(31 downto 16)*B2(31 downto 16) ;
            B7  := B4(31 downto 16)*B3(31 downto 16) ;
            B8  := B4(31 downto 16)*B4(31 downto 16) ;
            B9  := B8(31 downto 16)*H ;
            B10 := B8(31 downto 16)*B2(31 downto 16) ;
            B11 := B8(31 downto 16)*B3(31 downto 16) ;
            B12 := B8(31 downto 16)*B4(31 downto 16) ;
            B13 := B8(31 downto 16)*B5(31 downto 16) ;
            -- KEISU
            C1  := B1 ;
            C2  := '0' & B2(31 downto 17) ;
            B3  := B3(31 downto 16)*CONS3 ;
            C3  := B3(31 downto 16) ;
            C4  := "00" & B4(31 downto 18) ;
            B5  := B5(31 downto 16)*CONS5 ;
            C5  := B5(31 downto 16) ;
            B6  := B6(31 downto 16)*CONS3 ;
            C6  := '0' & B6(31 downto 17) ;
            B7  := B7(31 downto 16)*CONS7 ;
            C7  := B7(31 downto 16) ;
            C8  := "000" & B8(31 downto 19) ;
            B9  := B9(31 downto 16)*CONS9 ;
            C9  := B9(31 downto 16) ;
            B10 := B10(31 downto 16)*CONS5 ;
            C10 := '0' & B10(31 downto 17) ;
            B11 := B11(31 downto 16)*CONS11 ;
            C11 := B11(31 downto 16) ;
            B12 := B12(31 downto 16)*CONS3 ;
            C12 := "00" & B12(31 downto 18) ;
            B13 := B13(31 downto 16)*CONS13 ;
            C13 := B13(31 downto 16) ;
            -- KASAN
            D := C1+C2+C3+C4+C5+C6+C7+C8+C9+C10+C11+C12+C13 ;
            -- KEKKA
            Y <= D ;
        end if ;
    end process ;
-----------------------------------------------------------
-- output calculate                                      --
-----------------------------------------------------------
--Feb.14.2005 TAK
OUTPUT_CALC : process( M,G) -- N, Y )
    begin
       if( M = "00000000000000000000"  ) then
           Z <= (others=>'0') ;
       else
        --   F <= N * LOG2V ;
         --  G <= F - ("00000" & Y) ;
           Z <= G(19 downto 0) ;
        end if ;
   end process ;
F <= N * LOG2V ;
G <= F - ("00000" & Y) ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        Logalizm X (log(X))                                   --
// File         LOG.vhd                                               --
// Entity       LOG                                                   --
// rev date     coded contents                                        --
// 001 98/11/17 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  log ( x, z );
    
    input [19:0]  x ;
    output [19:0]  z ;


    reg [19:0] log_conv__tmp;
    reg [15:0] log_conv__h;
    reg [15:0] log_conv__b1;
    reg [31:0] log_conv__b2;
    reg [31:0] log_conv__b3;
    reg [31:0] log_conv__b4;
    reg [31:0] log_conv__b5;
    reg [31:0] log_conv__b6;
    reg [31:0] log_conv__b7;
    reg [31:0] log_conv__b8;
    reg [31:0] log_conv__b9;
    reg [31:0] log_conv__b10;
    reg [31:0] log_conv__b11;
    reg [31:0] log_conv__b12;
    reg [31:0] log_conv__b13;
    reg [15:0] log_conv__c1;
    reg [15:0] log_conv__c2;
    reg [15:0] log_conv__c3;
    reg [15:0] log_conv__c4;
    reg [15:0] log_conv__c5;
    reg [15:0] log_conv__c6;
    reg [15:0] log_conv__c7;
    reg [15:0] log_conv__c8;
    reg [15:0] log_conv__c9;
    reg [15:0] log_conv__c10;
    reg [15:0] log_conv__c11;
    reg [15:0] log_conv__c12;
    reg [15:0] log_conv__c13;
    reg [15:0] log_conv__d;
    parameter [15:0] log2v=16'b1011000101110010;
    parameter [15:0] cons3=16'b0101010101010101;
    parameter [15:0] cons5=16'b0011001100110011;
    parameter [15:0] cons7=16'b0010010010010010;
    parameter [15:0] cons9=16'b0001110001110001;
    parameter [15:0] cons11=16'b0001011101000101;
    parameter [15:0] cons13=16'b0001001110110001;
    parameter [15:0] cons15=16'b0001000100010001;
    reg [15:0] y;
    wire [20:0] f;
    wire [20:0] g;
    reg [19:0] m;
    reg [4:0] n;
    reg [19:0] z;


    
       
   always @ (x ) begin
           if ((x[19:0] === 20'b00000000000000000000)) 
               begin 
                   m <= {(19-0+1- 0){1'b0}};
                   n <= {(4-0+1- 0){1'b0}};
               end
               
           else 
               begin 
                   if ((x[19:1] === 19'b0000000000000000000)) 
                       begin 
                           m <= {x[0],19'b0000000000000000000};
                           n <= 5'b00001;
                       end
                       
                   else if ((x[19:2] === 18'b000000000000000000)) 
                       begin 
                           m <= {x[1:0],18'b000000000000000000};
                           n <= 5'b00010;
                       end
                       
                   else if ((x[19:3] === 17'b00000000000000000)) 
                       begin 
                           m <= {x[2:0],17'b00000000000000000};
                           n <= 5'b00011;
                       end
                       
                   else if ((x[19:4] === 16'b0000000000000000)) 
                       begin 
                           m <= {x[3:0],16'b0000000000000000};
                           n <= 5'b00100;
                       end
                       
                   else if ((x[19:5] === 15'b000000000000000)) 
                       begin 
                           m <= {x[4:0],15'b000000000000000};
                           n <= 5'b00101;
                       end
                       
                   else if ((x[19:6] === 14'b00000000000000)) 
                       begin 
                           m <= {x[5:0],14'b00000000000000};
                           n <= 5'b00110;
                       end
                       
                   else if ((x[19:7] === 13'b0000000000000)) 
                       begin 
                           m <= {x[6:0],13'b0000000000000};
                           n <= 5'b00111;
                       end
                       
                   else if ((x[19:8] === 12'b000000000000)) 
                       begin 
                           m <= {x[7:0],12'b000000000000};
                           n <= 5'b01000;
                       end
                       
                   else if ((x[19:9] === 11'b00000000000)) 
                       begin 
                           m <= {x[8:0],11'b00000000000};
                           n <= 5'b01001;
                       end
                       
                   else if ((x[19:10] === 10'b0000000000)) 
                       begin 
                           m <= {x[9:0],10'b0000000000};
                           n <= 5'b01010;
                       end
                       
                   else if ((x[19:11] === 9'b000000000)) 
                       begin 
                           m <= {x[10:0],9'b000000000};
                           n <= 5'b01011;
                       end
                       
                   else if ((x[19:12] === 8'b00000000)) 
                       begin 
                           m <= {x[11:0],8'b00000000};
                           n <= 5'b01100;
                       end
                       
                   else if ((x[19:13] === 7'b0000000)) 
                       begin 
                           m <= {x[12:0],7'b0000000};
                           n <= 5'b01101;
                       end
                       
                   else if ((x[19:14] === 6'b000000)) 
                       begin 
                           m <= {x[13:0],6'b000000};
                           n <= 5'b01110;
                       end
                       
                   else if ((x[19:15] === 5'b00000)) 
                       begin 
                           m <= {x[14:0],5'b00000};
                           n <= 5'b01111;
                       end
                       
                   else if ((x[19:16] === 4'b0000)) 
                       begin 
                           m <= {x[15:0],4'b0000};
                           n <= 5'b10000;
                       end
                       
                   else if ((x[19:17] === 3'b000)) 
                       begin 
                           m <= {x[16:0],3'b000};
                           n <= 5'b10001;
                       end
                       
                   else if ((x[19:18] === 2'b00)) 
                       begin 
                           m <= {x[17:0],2'b00};
                           n <= 5'b10010;
                       end
                       
                   else if ((x[19] === 1'b0)) 
                       begin 
                           m <= {x[18:0],1'b0};
                           n <= 5'b10011;
                       end
                       
                   else 
                       begin 
                           m <= x;
                           n <= 5'b10100;
                       end
                       
                   
                   
               end 
           
   end //always
   
       
   always @ (m ) begin
           if ((m === 20'b00000000000000000000)) 
               y <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   log_conv__tmp = (20'b00000000000000000000 - m);
                   log_conv__h = log_conv__tmp[19:4];
                   log_conv__b1 = log_conv__h;
                   log_conv__b2 = (log_conv__h * log_conv__h);
                   log_conv__b3 = (log_conv__b2[31:16] * log_conv__h);
                   log_conv__b4 = (log_conv__b2[31:16] * log_conv__b2[31:16]);
                   log_conv__b5 = (log_conv__b4[31:16] * log_conv__h);
                   log_conv__b6 = (log_conv__b4[31:16] * log_conv__b2[31:16]);
                   log_conv__b7 = (log_conv__b4[31:16] * log_conv__b3[31:16]);
                   log_conv__b8 = (log_conv__b4[31:16] * log_conv__b4[31:16]);
                   log_conv__b9 = (log_conv__b8[31:16] * log_conv__h);
                   log_conv__b10 = (log_conv__b8[31:16] * log_conv__b2[31:16]);
                   log_conv__b11 = (log_conv__b8[31:16] * log_conv__b3[31:16]);
                   log_conv__b12 = (log_conv__b8[31:16] * log_conv__b4[31:16]);
                   log_conv__b13 = (log_conv__b8[31:16] * log_conv__b5[31:16]);
                   log_conv__c1 = log_conv__b1;
                   log_conv__c2 = {1'b0,log_conv__b2[31:17]};
                   log_conv__b3 = (log_conv__b3[31:16] * cons3);
                   log_conv__c3 = log_conv__b3[31:16];
                   log_conv__c4 = {2'b00,log_conv__b4[31:18]};
                   log_conv__b5 = (log_conv__b5[31:16] * cons5);
                   log_conv__c5 = log_conv__b5[31:16];
                   log_conv__b6 = (log_conv__b6[31:16] * cons3);
                   log_conv__c6 = {1'b0,log_conv__b6[31:17]};
                   log_conv__b7 = (log_conv__b7[31:16] * cons7);
                   log_conv__c7 = log_conv__b7[31:16];
                   log_conv__c8 = {3'b000,log_conv__b8[31:19]};
                   log_conv__b9 = (log_conv__b9[31:16] * cons9);
                   log_conv__c9 = log_conv__b9[31:16];
                   log_conv__b10 = (log_conv__b10[31:16] * cons5);
                   log_conv__c10 = {1'b0,log_conv__b10[31:17]};
                   log_conv__b11 = (log_conv__b11[31:16] * cons11);
                   log_conv__c11 = log_conv__b11[31:16];
                   log_conv__b12 = (log_conv__b12[31:16] * cons3);
                   log_conv__c12 = {2'b00,log_conv__b12[31:18]};
                   log_conv__b13 = (log_conv__b13[31:16] * cons13);
                   log_conv__c13 = log_conv__b13[31:16];
                   log_conv__d = ((((((((((((log_conv__c1 + log_conv__c2) + log_conv__c3) + log_conv__c4) + log_conv__c5) + log_conv__c6) + log_conv__c7) + log_conv__c8) + log_conv__c9) + log_conv__c10) + log_conv__c11) + log_conv__c12) + log_conv__c13);
                   y <= log_conv__d;
               end
               
           
   end //always
   
       
   always @ (m or g ) begin
           if ((m === 20'b00000000000000000000)) 
               z <= {(19-0+1- 0){1'b0}};
               
           else 
               z <= g[19:0];
               
           
   end //always
   
   assign {f}=(n * log2v);
   
   assign {g}=(f - {5'b00000,y});
    

endmodule

//Feb.13.2005
//Feb.15.2005
//Tak.Sugawara
module cordic_bench_test;
    parameter cos_sin_mode=1'b0,atan_mode=1'b1;
    parameter integer bit_precision=10;//11 fails
    parameter integer atan_precision=11;//12 fails      
    parameter integer precision=bit_precision;//
    parameter real allowable_error=1.0/(2**precision);
    parameter real allowable_error_atan=1.0/(2**atan_precision);

    parameter integer scale_power=14;//bit
    parameter integer scale=2**scale_power;//16384
    parameter real max_test_angle_degree=91;//max of 100 degree 
    reg [15:0]  in_x=0 ;
    reg [15:0]  in_y=0 ;
    reg signed [15:0]  in_angle=0 ;
    reg in_start=0;
    reg in_mode=cos_sin_mode;
    reg clk=0;
    reg enable=0;
    reg xrst=0;
    wire out_finish;
    wire signed [15:0]  out_x ;
    wire signed [15:0]  out_y ;
    wire signed [15:0]  out_z ;

//
    real in_angle_r;
    real max_in_angle_r;//
    real hard_sin,hard_cos;//
    real max_angle_r;
    real h_sin_limit,l_sin_limit;
   
    real h_cos_limit,l_cos_limit;       
    integer i;
    real work,work1;
    real x_r,y_r,hard_z,angle_z;
        
        always #10 clk=~clk;

cordic dut ( in_x, in_y, in_angle, in_start, in_mode, clk, enable, xrst, out_finish, out_x, out_y, out_z );

        initial begin

//sin/cos test
//test  0->90degree
                repeat(2) @(posedge clk);
                @(negedge clk);
                 xrst=1;
                 in_start=1;
                 enable=1;
                begin :for_loop1
                  for (i=0; 1;i=i+1) begin 
                
                        in_angle=i;
                        @(negedge clk) in_start=0;
                        repeat(3) @(negedge clk);       
                        wait (out_finish);//wait hardware calculation
                        in_angle_r=$itor(in_angle)/$itor(scale);
                        hard_sin=$itor(out_y)/$itor(scale);
                        hard_cos=$itor(out_x)/$itor(scale);
                
                        work=$sin(in_angle_r);
                        work1=allowable_error;
                        h_sin_limit=$sin(in_angle_r)+allowable_error;//evaluate as output-bit-precision
                        l_sin_limit=$sin(in_angle_r)-allowable_error;
                
                        h_cos_limit=$cos(in_angle_r)+allowable_error;
                        l_cos_limit=$cos(in_angle_r)-allowable_error;
                        if (h_sin_limit  < hard_sin)begin
                                $display("sin max error detected %g %g",h_sin_limit,hard_sin);
                                $stop;
                        end             
                if (l_sin_limit > hard_sin) begin 
                                $display("sin min error detected %g %g",l_sin_limit,hard_sin);
                        end
                        if (h_cos_limit  < hard_cos)begin
                                $display("cos max error detected %g %g",h_cos_limit,hard_sin);
                                $stop;
                        end             
                if (l_cos_limit > hard_cos) begin 
                                $display("cos min error detected %g %g",l_cos_limit,hard_sin);
                        end
                        if (i%1000==0)
                        $display("i=%d in_angle_r=%g sin=%g hadware_result=%g",i,in_angle_r,$sin(in_angle_r),hard_sin);

                        max_angle_r=max_test_angle_degree/180.*$M_PI;
                        if (max_angle_r < in_angle_r) disable for_loop1;//exit test loop
                        @(negedge clk) in_start=1;
                end
             end //for loop
//test  0->-90degree
                @(negedge clk);
                  in_start=1;
                 enable=1;
                begin :for_loop2
                  for (i=0; 1;i=i+1) begin 
                
                        in_angle=-i;
                        @(negedge clk) in_start=0;
                        repeat(3) @(negedge clk);       
                        wait (out_finish);//wait hardware calculation
                        in_angle_r=$itor(in_angle)/$itor(scale);
                        hard_sin=$itor(out_y)/$itor(scale);
                        hard_cos=$itor(out_x)/$itor(scale);
                
                        work=$sin(in_angle_r);
                        work1=allowable_error;
                        h_sin_limit=$sin(in_angle_r)+allowable_error;//evaluate as output-bit-precision
                        l_sin_limit=$sin(in_angle_r)-allowable_error;
                
                        h_cos_limit=$cos(in_angle_r)+allowable_error;
                        l_cos_limit=$cos(in_angle_r)-allowable_error;
                        if (h_sin_limit  < hard_sin)begin
                                $display("sin max error detected %g %g",h_sin_limit,hard_sin);
                                $stop;
                        end             
                if (l_sin_limit > hard_sin) begin 
                                $display("sin min error detected %g %g",l_sin_limit,hard_sin);
                        end
                        if (h_cos_limit  < hard_cos)begin
                                $display("cos max error detected %g %g",h_cos_limit,hard_sin);
                                $stop;
                        end             
                if (l_cos_limit > hard_cos) begin 
                                $display("cos min error detected %g %g",l_cos_limit,hard_sin);
                        end
                        if (i%1000==0)
                        $display("i=%d in_angle_r=%g sin=%g hadware_result=%g",i,in_angle_r,$sin(in_angle_r),hard_sin);

                        max_angle_r=max_test_angle_degree/180.*$M_PI;
                        if (-max_angle_r > in_angle_r) disable for_loop2;//exit test loop
                        @(negedge clk) in_start=1;
                end
             end //for loop     

             $display("Cordic sin/cos test passed");            

//atan (y/x) 
//test scheme 
//   1>=x>0  assuming x**2+y**2=1  y=sqrt(1-xx*2);
//
                xrst=0;
                repeat(2) @(negedge clk);
                @(negedge clk);
                in_start=1;
                enable=1; 
                xrst=1; 
                in_mode=atan_mode;              
                for (i=0;i<= scale;i=i+1) begin                                 
                        in_x=i;//Start, with given in_x and in_y
                        x_r=$itor(i)/scale;
                        work=1.0-x_r**2;
                        y_r=$sqrt(work);
                        work1=y_r*scale;
                        in_y=$rtoi(work1);
                        @(negedge clk) in_start=0;//deassert _instart
                        repeat(3) @(negedge clk);       
                        wait (out_finish);//wait hardware calculation
                        @(negedge clk);
                        hard_z=$itor(out_z)/scale;//get hardware result.
                        if (i==0) angle_z=$M_PI/2.0;
                        else if (i==scale) angle_z=0.0;
                        else angle_z=$atan(y_r/x_r);
                        if (hard_z > angle_z+allowable_error_atan) begin
                                 $display("Error Detected atan max");
                                 $stop;//assert(0);
                        end
                        if (hard_z < angle_z-allowable_error_atan) begin 
                                $display("Error Detected atan min");
                                $stop;//assert(0);
                        end
                        @(negedge clk) in_start=1;
                end
                $display("atan(y/x) test passed");
                $finish;
        end
endmodule

------------------------------------------------------------------------
-- Title        CORDIC calculater sin(x), cos(x), atan(y/x)           --
-- File         CORDIC.vhd                                            --
-- Entity       CORDIC                                                --
-- rev date     coded contents                                        --
-- 001 99/01/06 ueno  Make Original                                   --
------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
--use IEEE.std_logic_signed.all ;
--use IEEE.std_logic_arith.all ;

------------------------------------------------------------------------
-- entity                                                             --
------------------------------------------------------------------------
entity CORDIC is
    port(
        -- Input/Output Data format = Fixed Point Value
        --     range -1.99994 to 1.99994 2's complement
        -- 15  14 . 13  12  11  10  09  08  07  06  05  04  03  02  01  00
        -- Sign   ^point
        --
        IN_X        : in    std_logic_vector(15 downto 0) ; -- atan(y/X)    -0.15 to 1.00
        IN_Y        : in    std_logic_vector(15 downto 0) ; -- atan(Y/x)    -1.00 to 1.00
        IN_ANGLE    : in    std_logic_vector(15 downto 0) ; -- angle(thita) -1.74 to 1.74
        IN_START    : in    std_logic ;                     -- convert start
        IN_MODE     : in    std_logic ;                     -- 1=atan/0=sin,cos
        CLK         : in    std_logic ;                     -- System Clock
        ENABLE      : in    std_logic ;                     -- Clock Enable
        XRST        : in    std_logic ;                     -- Reset
        OUT_FINISH  : out   std_logic ;                     -- Convert end
        OUT_X       : out   std_logic_vector(15 downto 0) ; -- Calculate X
        OUT_Y       : out   std_logic_vector(15 downto 0) ; -- Calculate Y
        OUT_Z       : out   std_logic_vector(15 downto 0)   -- Calculate Z
    );
end CORDIC ;

------------------------------------------------------------------------
-- architecture                                                       --
------------------------------------------------------------------------
architecture RTL of CORDIC is

--constant    ENABLE  : std_logic := '1' ;

-----------------------------------------------------------
-- Constants                                             --
-----------------------------------------------------------
constant    VAL0    : std_logic_vector(15 downto 0) := "0000000000000000" ; -- 0.000000000
constant    VALX    : std_logic_vector(15 downto 0) := "0010011011011101" ; -- 0.607252935
constant    ATAN00  : std_logic_vector(15 downto 0) := "0011001001000100" ; -- atan(1/1)
constant    ATAN01  : std_logic_vector(15 downto 0) := "0001110110101100" ; -- atan(1/2)
constant    ATAN02  : std_logic_vector(15 downto 0) := "0000111110101110" ; -- atan(1/4)
constant    ATAN03  : std_logic_vector(15 downto 0) := "0000011111110101" ; -- atan(1/8)
constant    ATAN04  : std_logic_vector(15 downto 0) := "0000001111111111" ; -- atan(1/16)
constant    ATAN05  : std_logic_vector(15 downto 0) := "0000001000000000" ; -- atan(1/32)
constant    ATAN06  : std_logic_vector(15 downto 0) := "0000000100000000" ; -- atan(1/64)
constant    ATAN07  : std_logic_vector(15 downto 0) := "0000000010000000" ; -- atan(1/128)
constant    ATAN08  : std_logic_vector(15 downto 0) := "0000000001000000" ; -- atan(1/256)
constant    ATAN09  : std_logic_vector(15 downto 0) := "0000000000100000" ; -- atan(1/512)
constant    ATAN10  : std_logic_vector(15 downto 0) := "0000000000010000" ; -- atan(1/1024)
constant    ATAN11  : std_logic_vector(15 downto 0) := "0000000000001000" ; -- atan(1/2048)
constant    ATAN12  : std_logic_vector(15 downto 0) := "0000000000000100" ; -- atan(1/4096)
constant    ATAN13  : std_logic_vector(15 downto 0) := "0000000000000010" ; -- atan(1/8192)
constant    ATAN14  : std_logic_vector(15 downto 0) := "0000000000000001" ; -- atan(1/16384)
constant    ATAN15  : std_logic_vector(15 downto 0) := "0000000000000000" ; -- atan(1/32768)

-----------------------------------------------------------
-- Signals                                               --
-----------------------------------------------------------
signal  REG_X       : std_logic_vector(15 downto 0) ;   -- Xn Register
signal  REG_Y       : std_logic_vector(15 downto 0) ;   -- Yn Register
signal  REG_Z       : std_logic_vector(15 downto 0) ;   -- Zn Register
signal  REG_J       : std_logic_vector(3 downto 0)  ;   -- 0 to 15 counter

signal  AX          : std_logic_vector(15 downto 0) ;   -- Ballel Shift X
signal  BX          : std_logic_vector(15 downto 0) ;   -- Ballel Shift X
signal  CX          : std_logic_vector(15 downto 0) ;   -- Ballel Shift X
signal  DX          : std_logic_vector(15 downto 0) ;   -- Ballel Shift X
signal  AY          : std_logic_vector(15 downto 0) ;   -- Ballel Shift Y
signal  BY          : std_logic_vector(15 downto 0) ;   -- Ballel Shift Y
signal  CY          : std_logic_vector(15 downto 0) ;   -- Ballel Shift Y
signal  DY          : std_logic_vector(15 downto 0) ;   -- Ballel Shift Y
signal  TAB_Z       : std_logic_vector(15 downto 0) ;   -- Table Select Z

signal  INIT_LOAD   : std_logic ;                       -- X,Y,Z Initialize
signal  NOW_CONVERT : std_logic ;                       -- Now Conveting for CORDIC

signal  ADD_SUB     : std_logic ;                       -- Next Calculate '1'=ADD/'0'=SUB

-----------------------------------------------------------
-- Architectures                                         --
-----------------------------------------------------------
begin

-----------------------------------------------------------
-- Flag Control                                          --
-----------------------------------------------------------
INIT_FLAG       : process( CLK, XRST )
    begin
        if( XRST='0' ) then
            INIT_LOAD <= '0' ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                if( IN_START='1' and INIT_LOAD='0' and NOW_CONVERT='0' ) then
                    INIT_LOAD <= '1' ;
                else
                    INIT_LOAD <= '0' ;
                end if ;
            end if ;
        end if ;
    end process ;
CONVERT_FLAG    : process( CLK, XRST )
    begin
        if( XRST='0' ) then
            NOW_CONVERT <= '0' ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                if( INIT_LOAD='1' ) then
                    NOW_CONVERT <= '1' ;
                elsif( REG_J="1111" ) then
                    NOW_CONVERT <= '0' ;
                end if ;
            end if ;
        end if ;
    end process ;

-----------------------------------------------------------
-- Sequence Counter                                      --
-----------------------------------------------------------
COUNTER_GEN     : process( CLK, XRST )
    begin
        if( XRST='0' ) then
            REG_J <= "0000" ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                if( NOW_CONVERT='1' ) then
                    REG_J <= REG_J + 1 ;
                end if ;
            end if ;
        end if ;
    end process ;

-----------------------------------------------------------
-- ADD/SUB Flag                                          --
-----------------------------------------------------------
SELECT_ADD_SUB  : ADD_SUB <= not REG_Y(15) when IN_MODE='1' else REG_Z(15) ;

-----------------------------------------------------------
-- Ballel Shifter                                        --
-----------------------------------------------------------
BALLEL_AX       : process( REG_X, REG_J )
    begin
        if( REG_J(3)='1' ) then
            AX <= REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15) & REG_X(15 downto 8);
        else
            AX <= REG_X ;
        end if ;
    end process ;
BALLEL_BX       : process( AX, REG_J )
    begin
        if( REG_J(2)='1' ) then
            BX <= AX(15) & AX(15) & AX(15) & AX(15) & AX(15 downto 4);
        else
            BX <= AX ;
        end if ;
    end process ;
BALLEL_CX       : process( BX, REG_J )
    begin
        if( REG_J(1)='1' ) then
            CX <= BX(15) & BX(15) & BX(15 downto 2);
        else
            CX <= BX ;
        end if ;
    end process ;
BALLEL_DX       : process( CX, REG_J )
    begin
        if( REG_J(0)='1' ) then
            DX <= CX(15) & CX(15 downto 1);
        else
            DX <= CX ;
        end if ;
    end process ;
BALLEL_AY       : process( REG_Y, REG_J )
    begin
        if( REG_J(3)='1' ) then
            AY <= REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15) & REG_Y(15 downto 8);
        else
            AY <= REG_Y ;
        end if ;
    end process ;
BALLEL_BY       : process( AY, REG_J )
    begin
        if( REG_J(2)='1' ) then
            BY <= AY(15) & AY(15) & AY(15) & AY(15) & AY(15 downto 4);
        else
            BY <= AY ;
        end if ;
    end process ;
BALLEL_CY       : process( BY, REG_J )
    begin
        if( REG_J(1)='1' ) then
            CY <= BY(15) & BY(15) & BY(15 downto 2);
        else
            CY <= BY ;
        end if ;
    end process ;
BALLEL_DY       : process( CY, REG_J )
    begin
        if( REG_J(0)='1' ) then
            DY <= CY(15) & CY(15 downto 1);
        else
            DY <= CY ;
        end if ;
    end process ;
TABLE_Z         : process( REG_J )
    begin
        case REG_J is
            when "0000" => TAB_Z <= ATAN00 ;
            when "0001" => TAB_Z <= ATAN01 ;
            when "0010" => TAB_Z <= ATAN02 ;
            when "0011" => TAB_Z <= ATAN03 ;
            when "0100" => TAB_Z <= ATAN04 ;
            when "0101" => TAB_Z <= ATAN05 ;
            when "0110" => TAB_Z <= ATAN06 ;
            when "0111" => TAB_Z <= ATAN07 ;
            when "1000" => TAB_Z <= ATAN08 ;
            when "1001" => TAB_Z <= ATAN09 ;
            when "1010" => TAB_Z <= ATAN10 ;
            when "1011" => TAB_Z <= ATAN11 ;
            when "1100" => TAB_Z <= ATAN12 ;
            when "1101" => TAB_Z <= ATAN13 ;
            when "1110" => TAB_Z <= ATAN14 ;
            when "1111" => TAB_Z <= ATAN15 ;
            when others => TAB_Z <= VAL0 ;
        end case ;
    end process ;

-----------------------------------------------------------
-- Calculate                                             --
-----------------------------------------------------------
CALC_X          : process( CLK, XRST )
    begin
        if( XRST='0') then
            REG_X <= (others=>'0') ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                -- Initial Value
                if( INIT_LOAD = '1' ) then
                    if( IN_MODE='1' ) then
                        -- Atan Mode
                        REG_X <= IN_X ;
                    else
                        -- Sin/Cos Mode
                        REG_X <= VALX ;
                    end if ;
                elsif( NOW_CONVERT='1' ) then
                    if( ADD_SUB='1' ) then
                        REG_X <= REG_X + DY ;
                    else
                        REG_X <= REG_X - DY ;
                    end if ;
                end if ;
            end if ;
        end if ;
    end process ;
CALC_Y          : process( CLK, XRST )
    begin
        if( XRST='0') then
            REG_Y <= (others=>'0') ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                -- Initial Value
                if( INIT_LOAD = '1' ) then
                    if( IN_MODE='1' ) then
                        -- Atan Mode
                        REG_Y <= IN_Y ;
                    else
                        -- Sin/Cos Mode
                        REG_Y <= VAL0 ;
                    end if ;
                elsif( NOW_CONVERT='1' ) then
                    if( ADD_SUB='1' ) then
                        REG_Y <= REG_Y - DX ;
                    else
                        REG_Y <= REG_Y + DX ;
                    end if ;
                end if ;
            end if ;
        end if ;
    end process ;
CALC_Z          : process( CLK, XRST )
    begin
        if( XRST='0') then
            REG_Z <= (others=>'0') ;
        elsif( CLK'event and CLK='1' ) then
            if( ENABLE='1' ) then
                -- Initial Value
                if( INIT_LOAD = '1' ) then
                    if( IN_MODE='1' ) then
                        -- Atan Mode
                        REG_Z <= VAL0 ;
                    else
                        -- Sin/Cos Mode
                        REG_Z <= IN_ANGLE ;
                    end if ;
                elsif( NOW_CONVERT='1' ) then
                    if( ADD_SUB='1' ) then
                        REG_Z <= REG_Z + TAB_Z ;
                    else
                        REG_Z <= REG_Z - TAB_Z ;
                    end if ;
                end if ;
            end if ;
        end if ;
    end process ;

OUT_FINISH <= not NOW_CONVERT ;
OUT_X      <= REG_X ;
OUT_Y      <= REG_Y ;
OUT_Z      <= REG_Z ;

end RTL ;
------------------------------------------------------------------------
-- End of File                                                        --
------------------------------------------------------------------------

//-------------------------------------------------------------------
//
//   This file is automatically generated by VHDL to Verilog Translator.
//         Ver.1.08 Build Mar.6.2004
//               www.sugawara-systems.com   
//                    tech-support@sugawara-systems.com
//        See Original Copyright Notice for property of the file .( somewhere in this file.)
//
//--------------------------------------------------------------------


//----------------------------------------------------------------------
// Title        CORDIC calculater sin(x), cos(x), atan(y/x)           --
// File         CORDIC.vhd                                            --
// Entity       CORDIC                                                --
// rev date     coded contents                                        --
// 001 99/01/06 ueno  Make Original                                   --
//----------------------------------------------------------------------

`timescale 1ns/1ns
`define ns 1
`define us (1000*`ns)
`define ms (1000*`us)
`define sec (1000*`ms)

module  cordic ( in_x, in_y, in_angle, in_start, in_mode, clk, enable, xrst, out_finish, out_x, out_y, out_z );
    
    input [15:0]  in_x ;
    input [15:0]  in_y ;
    input [15:0]  in_angle ;
    input in_start;
    input in_mode;
    input clk;
    input enable;
    input xrst;
    output out_finish;
    output [15:0]  out_x ;
    output [15:0]  out_y ;
    output [15:0]  out_z ;


    parameter [15:0] val0=16'b0000000000000000;
    parameter [15:0] valx=16'b0010011011011101;
    parameter [15:0] atan00=16'b0011001001000100;
    parameter [15:0] atan01=16'b0001110110101100;
    parameter [15:0] atan02=16'b0000111110101110;
    parameter [15:0] atan03=16'b0000011111110101;
    parameter [15:0] atan04=16'b0000001111111111;
    parameter [15:0] atan05=16'b0000001000000000;
    parameter [15:0] atan06=16'b0000000100000000;
    parameter [15:0] atan07=16'b0000000010000000;
    parameter [15:0] atan08=16'b0000000001000000;
    parameter [15:0] atan09=16'b0000000000100000;
    parameter [15:0] atan10=16'b0000000000010000;
    parameter [15:0] atan11=16'b0000000000001000;
    parameter [15:0] atan12=16'b0000000000000100;
    parameter [15:0] atan13=16'b0000000000000010;
    parameter [15:0] atan14=16'b0000000000000001;
    parameter [15:0] atan15=16'b0000000000000000;
    reg [15:0] reg_x;
    reg [15:0] reg_y;
    reg [15:0] reg_z;
    reg [3:0] reg_j;
    reg [15:0] ax;
    reg [15:0] bx;
    reg [15:0] cx;
    reg [15:0] dx;
    reg [15:0] ay;
    reg [15:0] by;
    reg [15:0] cy;
    reg [15:0] dy;
    reg [15:0] tab_z;
    reg init_load;
    reg now_convert;
    wire add_sub;
    wire out_finish;
    wire [15:0] out_x;
    wire [15:0] out_y;
    wire [15:0] out_z;


    
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               init_load <= 1'b0;
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((((in_start === 1'b1) & (init_load === 1'b0)) & (now_convert === 1'b0))) 
                                       init_load <= 1'b1;
                               else 
                                       init_load <= 1'b0;

                               
                       end 
                   
                   
               end 
           
   end //always
   
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               now_convert <= 1'b0;
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((init_load === 1'b1)) 
                                       now_convert <= 1'b1;
                               else if ((reg_j === 4'b1111)) 
                                       now_convert <= 1'b0;

                               
                       end 
                   
                   
               end 
           
   end //always
   
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               reg_j <= 4'b0000;
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((now_convert === 1'b1)) 
                                       reg_j <= (reg_j + 1);

                               
                       end 
                   
                   
               end 
           
   end //always
   
   assign {add_sub}=(in_mode === 1'b1) ? 
                        ~ (reg_y[15])
                     :  reg_z[15];
   
       
   always @ (reg_x or reg_j ) begin
           if ((reg_j[3] === 1'b1)) 
               ax <= {{{{{{{{reg_x[15],reg_x[15]},reg_x[15]},reg_x[15]},reg_x[15]},reg_x[15]},reg_x[15]},reg_x[15]},reg_x[15:8]};
               
           else 
               ax <= reg_x;
               
           
   end //always
   
       
   always @ (ax or reg_j ) begin
           if ((reg_j[2] === 1'b1)) 
               bx <= {{{{ax[15],ax[15]},ax[15]},ax[15]},ax[15:4]};
               
           else 
               bx <= ax;
               
           
   end //always
   
       
   always @ (bx or reg_j ) begin
           if ((reg_j[1] === 1'b1)) 
               cx <= {{bx[15],bx[15]},bx[15:2]};
               
           else 
               cx <= bx;
               
           
   end //always
   
       
   always @ (cx or reg_j ) begin
           if ((reg_j[0] === 1'b1)) 
               dx <= {cx[15],cx[15:1]};
               
           else 
               dx <= cx;
               
           
   end //always
   
       
   always @ (reg_y or reg_j ) begin
           if ((reg_j[3] === 1'b1)) 
               ay <= {{{{{{{{reg_y[15],reg_y[15]},reg_y[15]},reg_y[15]},reg_y[15]},reg_y[15]},reg_y[15]},reg_y[15]},reg_y[15:8]};
               
           else 
               ay <= reg_y;
               
           
   end //always
   
       
   always @ (ay or reg_j ) begin
           if ((reg_j[2] === 1'b1)) 
               by <= {{{{ay[15],ay[15]},ay[15]},ay[15]},ay[15:4]};
               
           else 
               by <= ay;
               
           
   end //always
   
       
   always @ (by or reg_j ) begin
           if ((reg_j[1] === 1'b1)) 
               cy <= {{by[15],by[15]},by[15:2]};
               
           else 
               cy <= by;
               
           
   end //always
   
       
   always @ (cy or reg_j ) begin
           if ((reg_j[0] === 1'b1)) 
               dy <= {cy[15],cy[15:1]};
               
           else 
               dy <= cy;
               
           
   end //always
   
       
   always @ (reg_j ) begin
           case (reg_j)
               4'b0000 : 
                       tab_z <= 16'b0011001001000100;
               4'b0001 : 
                       tab_z <= 16'b0001110110101100;
               4'b0010 : 
                       tab_z <= 16'b0000111110101110;
               4'b0011 : 
                       tab_z <= 16'b0000011111110101;
               4'b0100 : 
                       tab_z <= 16'b0000001111111111;
               4'b0101 : 
                       tab_z <= 16'b0000001000000000;
               4'b0110 : 
                       tab_z <= 16'b0000000100000000;
               4'b0111 : 
                       tab_z <= 16'b0000000010000000;
               4'b1000 : 
                       tab_z <= 16'b0000000001000000;
               4'b1001 : 
                       tab_z <= 16'b0000000000100000;
               4'b1010 : 
                       tab_z <= 16'b0000000000010000;
               4'b1011 : 
                       tab_z <= 16'b0000000000001000;
               4'b1100 : 
                       tab_z <= 16'b0000000000000100;
               4'b1101 : 
                       tab_z <= 16'b0000000000000010;
               4'b1110 : 
                       tab_z <= 16'b0000000000000001;
               4'b1111 : 
                       tab_z <= 16'b0000000000000000;
               default : 
                       tab_z <= 16'b0000000000000000;
           endcase
   end //always
   
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               reg_x <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((init_load === 1'b1)) 
                                   begin 
                                           if ((in_mode === 1'b1)) 
                                                   reg_x <= in_x;
                                           else 
                                                   reg_x <= 16'b0010011011011101;

                                           
                                   end 
                               else if ((now_convert === 1'b1)) 
                                   begin 
                                           if ((add_sub === 1'b1)) 
                                                   reg_x <= (reg_x + dy);
                                           else 
                                                   reg_x <= (reg_x - dy);

                                           
                                   end 

                               
                       end 
                   
                   
               end 
           
   end //always
   
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               reg_y <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((init_load === 1'b1)) 
                                   begin 
                                           if ((in_mode === 1'b1)) 
                                                   reg_y <= in_y;
                                           else 
                                                   reg_y <= 16'b0000000000000000;

                                           
                                   end 
                               else if ((now_convert === 1'b1)) 
                                   begin 
                                           if ((add_sub === 1'b1)) 
                                                   reg_y <= (reg_y - dx);
                                           else 
                                                   reg_y <= (reg_y + dx);

                                           
                                   end 

                               
                       end 
                   
                   
               end 
           
   end //always
   
       
   always @ (posedge clk or negedge xrst ) begin
           if ((xrst === 1'b0)) 
               reg_z <= {(15-0+1- 0){1'b0}};
               
           else 
               begin 
                   if ((enable === 1'b1)) 
                       begin 
                               if ((init_load === 1'b1)) 
                                   begin 
                                           if ((in_mode === 1'b1)) 
                                                   reg_z <= 16'b0000000000000000;
                                           else 
                                                   reg_z <= in_angle;

                                           
                                   end 
                               else if ((now_convert === 1'b1)) 
                                   begin 
                                           if ((add_sub === 1'b1)) 
                                                   reg_z <= (reg_z + tab_z);
                                           else 
                                                   reg_z <= (reg_z - tab_z);

                                           
                                   end 

                               
                       end 
                   
                   
               end 
           
   end //always
   
   assign {out_finish}=~ (now_convert);
   
   assign {out_x}=reg_x;
   
   assign {out_y}=reg_y;
   
   assign {out_z}=reg_z;
    

endmodule