15.BNF
Verilog1995ベースでのVeritakサポート構文です。サポートしていない構文は赤字になってます。Verision3.26A時点です。(Jan.10.2007 更新)
BNFの見方
項 | |
空白スペース | トークン(文字列の切り出し単位)の区切りで使用 |
< > | アイテムのくくり記号で、実際のソース上では現れない。 |
<name>(小文字) | 文法を構成するアイテム |
<NAME>(大文字) | トークン |
<name>? | あってもなくてもよい |
<name>* | 0または1個以上の項目 |
<name>+ | 1個以上の項目 |
<name><,<name>>* | カンマで分離された少なくとも一個以上の項目 |
<name>::= | 構文定義 |
||= | 構文の別定義 |
<source_text>
::= <description>*
<description>
::= <module>
||= <UDP>
<module>
::= module <name_of_module> <list_of_ports>? ;
<module_item>*
endmodule
||= macromodule <name_of_module> <list_of_ports>? ;
<module_item>*
endmodule
<name_of_module>
::= <IDENTIFIER>
<list_of_ports>
::= ( <port> <,<port>>* )
<port>
::= <port_expression>?
||= . <name_of_port> ( <port_expression>? )
<port_expression>
::= <port_reference>
||= { <port_reference> <,<port_reference>>* }
<port_reference>
::= <name_of_variable>
||= <name_of_variable> [ <constant_expression> ]
||= <name_of_variable> [ <constant_expression> :<constant_expression> ]
<name_of_port>
::= <IDENTIFIER>
<name_of_variable>
::= <IDENTIFIER>
<module_item>
::= <parameter_declaration>
||= <input_declaration>
||= <output_declaration>
||= <inout_declaration>
||= <net_declaration>
||= <reg_declaration>
||= <time_declaration>
||= <integer_declaration>
||= <real_declaration>
||= <event_declaration>
||= <gate_declaration>
||= <UDP_instantiation>
||= <module_instantiation>
||= <parameter_override>
||= <continuous_assign>
||= <specify_block>
||= <initial_statement>
||= <always_statement>
||= <task>
||= <function>
<UDP>
::= primitive <name_of_UDP> ( <name_of_variable>
<,<name_of_variable>>* ) ;
<UDP_declaration>+
<UDP_initial_statement>?
<table_definition>
endprimitive
<name_of_UDP>
::= <IDENTIFIER>
<UDP_declaration>
::= <output_declaration>
||= <reg_declaration>
||= <input_declaration>
<UDP_initial_statement>
::= initial <output_terminal_name> = <init_val> ;
<init_val>
::= 1'b0
||= 1'b1
||= 1'bx
||= 1'bX
||= 1'B0
||= 1'B1
||= 1'Bx
||= 1'BX
||= 1
||= 0
<output_terminal_name>
::= <name_of_variable>
<table_definition>
::= table <table_entries> endtable
<table_entries>
::= <combinational_entry>+
||= <sequential_entry>+
<combinational_entry>
::= <level_input_list> : <OUTPUT_SYMBOL> ;
<sequential_entry>
::= <input_list> : <state> : <next_state> ;
<input_list>
::= <level_input_list>
||= <edge_input_list>
<level_input_list>
::= <LEVEL_SYMBOL>+
<edge_input_list>
::= <LEVEL_SYMBOL>* <edge> <LEVEL_SYMBOL>*
<edge>
::= ( <LEVEL_SYMBOL> <LEVEL_SYMBOL> )
||= <EDGE_SYMBOL>
<state>
::= <LEVEL_SYMBOL>
<next_state>
::= <OUTPUT_SYMBOL>
||= - (リテラルハイフン)
<OUTPUT_SYMBOL>
0 1 x X
<LEVEL_SYMBOL>
0 1 x X ? b B
<EDGE_SYMBOL>
r R f F p P n N *
<task>
::= task <name_of_task> ;
<tf_declaration>*
<statement_or_null>
endtask
<name_of_task>
::= <IDENTIFIER>
<function>
::= function <range_or_type>? <name_of_function> ;
<tf_declaration>+
<statement>
endfunction
<range_or_type>
::= <range>
||= integer
||= real
<name_of_function>
::= <IDENTIFIER>
<tf_declaration>
::= <parameter_declaration>
||= <input_declaration>
||= <output_declaration>
||= <inout_declaration>
||= <reg_declaration>
||= <time_declaration>
||= <integer_declaration>
||= <real_declaration>
<parameter_declaration>
::= parameter <list_of_param_assignments> ;
<list_of_param_assignments>
::=<param_assignment><,<param_assignment>*
<param_assignment>
::=<identifier> = <constant_expression>
<input_declaration>
::= input <range>? <list_of_variables> ;
<output_declaration>
::= output <range>? <list_of_variables> ;
<inout_declaration>
::= inout <range>? <list_of_variables> ;
<net_declaration>
::= <NETTYPE> <expandrange>? <delay>? <list_of_variables> ;
||= trireg <charge_strength>? <expandrange>? <delay>?
<list_of_variables> ;
||= <NETTYPE> <drive_strength>? <expandrange>? <delay>? <list_of_assignments> ;
<NETTYPE> keywords:
wire tri tri1 supply0 wand triand tri0 supply1 wor trior trireg
<expandrange>
::= <range>
||= scalared <range>
||= vectored <range>
<reg_declaration>
::= reg <range>? <list_of_register_variables> ;
<time_declaration>
::= time <list_of_register_variables> ;
<integer_declaration>
::= integer <list_of_register_variables> ;
<real_declaration>
::= real <list_of_variables> ;
<event_declaration>
::= event <name_of_event> <,<name_of_event>>* ;
<continuous_assign>
::= assign <drive_strength>? <delay>? <list_of_assignments> ;
||= <NETTYPE> <drive_strength>? <expandrange>? <delay>? <list_of_assignments> ;
<parameter_override>
::= defparam <list_of_param_assignments> ;
<list_of_variables>
::= <name_of_variable> <,<name_of_variable>>*
<name_of_variable>
::= <IDENTIFIER>
<list_of_register_variables>
::= <register_variable> <,<register_variable>>*
<register_variable>
::= <name_of_register>
||= <name_of_memory> [ <constant_expression> : <constant_expression> ]
<name_of_register>
::= <IDENTIFIER>
<name_of_memory>
::= <IDENTIFIER>
<name_of_event>
::= <IDENTIFIER>
<charge_strength>
::= ( small )
||= ( medium )
||= ( large )
<drive_strength>
::= ( <STRENGTH0> , <STRENGTH1> )
||= ( <STRENGTH1> , <STRENGTH0> )
<STRENGTH0> keywords:
supply0 strong0 pull0 weak0 highz0
<STRENGTH1> keywords:
supply1 strong1 pull1 weak1 highz1
<range>
::= [ <constant_expression> : <constant_expression> ]
<list_of_assignments>
::= <assignment> <,<assignment>>*
<gate_declaration>
::= <GATETYPE> <drive_strength>? <delay>? <gate_instance> <,<gate_instance>>* ;
<GATETYPE> keywords:and nand or nor xor xnor buf bufif0 bufif1 not notif0 notif1 pulldown pullup
nmos rnmos pmos rpmos cmos rcmos tran rtran tranif0 rtranif0 tranif1 rtranif1
<delay>
::= # <number>
||= # <identifier>
||= # (<mintypmax_expression> <,<mintypmax_expression>>? <,<mintypmax_expression>>?)
<gate_instance>
::= <name_of_gate_instance>? ( <terminal> <,<terminal>>* )
<name_of_gate_instance>
::= <IDENTIFIER><range>?
<UDP_instantiation>
::= <name_of_UDP> <drive_strength>? <delay>?
<UDP_instance> <,<UDP_instance>>* ;
<name_of_UDP>
::= <IDENTIFIER>
<UDP_instance>
::= <name_of_UDP_instance>? ( <terminal> <,<terminal>>* )
<name_of_UDP_instance>
::= <IDENTIFIER><range>?
<terminal>
::= <expression>
||= <IDENTIFIER>
<module_instantiation> ::= <name_of_module> <parameter_value_assignment>? <module_instance> <,<module_instance>>* ; <name_of_module> ::= <IDENTIFIER> <parameter_value_assignment> ::= # ( <expression> <,<expression>>* ) <module_instance> ::= <name_of_instance> ( <list_of_module_connections>? ) <name_of_instance> ::= <IDENTIFIER><range>? <list_of_module_connections> ::= <module_port_connection> <,<module_port_connection>>* ||= <named_port_connection> <,<named_port_connection>>* <module_port_connection> ::= <expression> ||= <NULL> <NULL> ::= たとえば、次の例でもよい。 (a, b, , d) <named_port_connection> ::= .< IDENTIFIER> ( <expression> )
<initial_statement>
::= initial <statement>
<always_statement>
::= always <statement>
<statement_or_null>
::= <statement>
||= ;
<statement>
::=<blocking_assignment> ;
||= <non_blocking_assignment> ;
||= if ( <expression> ) <statement_or_null>
||= if ( <expression> ) <statement_or_null> else <statement_or_null>
||= case ( <expression> ) <case_item>+ endcase
||= casez ( <expression> ) <case_item>+ endcase
||= casex ( <expression> ) <case_item>+ endcase
||= forever <statement>
||= repeat ( <expression> ) <statement>
||= while ( <expression> ) <statement>
||= for ( <assignment> ; <expression> ; <assignment> ) <statement>
||= <delay_or_event_control> <statement_or_null>
||= wait ( <expression> ) <statement_or_null>
||= -> <name_of_event> ;
||= <seq_block>
||= <par_block>
||= <task_enable>
||= <system_task_enable>
||= disable <name_of_task> ;
||= disable <name_of_block> ;
||= assign <assignment> ;
||= deassign <lvalue> ;
||= force <assignment> ;
||= release <lvalue> ;
<assignment>
::= <lvalue> = <expression>
<blocking_assignment>
::= <lvalue> = <expression>
||= <lvalue> = <delay_or_event_control> <expression> ;
<non_blocking_assignment>
::= <lvalue> <= <expression>
||= <lvalue> = <delay_or_event_control> <expression> ;
(メモリに対するEVENT_CONTROLは、未サポート、Multi-NamedEventは未サポート)
<delay_or_event_control>
::= <delay_control>
||= <event_control>
||= repeat ( <expression> ) <event_control>
<case_item>
::= <expression> <,<expression>>* : <statement_or_null>
||= default : <statement_or_null>
||= default <statement_or_null>
<seq_block>
::= begin <statement>* end
||= begin : <name_of_block> <block_declaration>* <statement>* end
<par_block>
::= fork <statement>* join
||= fork : <name_of_block> <block_declaration>* <statement>* join
<name_of_block>
::= <IDENTIFIER>
<block_declaration>
::= <parameter_declaration>
||= <reg_declaration>
||= <integer_declaration>
||= <real_declaration>
||= <time_declaration>
||= <event_declaration>
<task_enable>
::= <name_of_task>
||= <name_of_task> ( <expression> <,<expression>>* ) ;
<system_task_enable>
::= <name_of_system_task> ;
||= <name_of_system_task> ( <expression> <,<expression>>* ) ;
<name_of_system_task>
::= $<system_identifier>
<SYSTEM_IDENTIFIER>
An <IDENTIFIER>
<specify_block>
::= specify <specify_item>* endspecify
<specify_item>
::= <specparam_declaration>
||= <path_declaration>
||= <level_sensitive_path_declaration>
||= <edge_sensitive_path_declaration>
||= <system_timing_check>
||= <sdpd>
<specparam_declaration>
::= specparam <list_of_param_assignments> ;
<list_of_param_assignments>
::=<param_assignment><,<param_assignment>>*
<param_assignment>
::=<<identifier>=<constant_expression>>
<path_declaration>
::= <path_description> = <path_delay_value> ;
<path_description>
::= ( <specify_input_terminal_descriptor> => <specify_output_terminal_descriptor> )
||= ( <list_of_path_inputs> *> <list_of_path_outputs> )
<list_of_path_inputs>
::= <specify_input_terminal_descriptor> <,<specify_input_terminal_descriptor>>*
<list_of_path_outputs>
::= <specify_output_terminal_descriptor> <,<specify_output_terminal_descriptor>>*
<specify_input_terminal_descriptor>
::= <input_identifier>
||= <input_identifier> [ <constant_expression> ]
||= <input_identifier> [ <constant_expression> : <constant_expression> ]
<specify_output_terminal_descriptor>
::= <output_identifier>
||= <output_identifier> [ <constant_expression> ]
||= <output_identifier> [ <constant_expression> : <constant_expression> ]
<input_identifier>
::= the <IDENTIFIER> of a module input or inout terminal
<output_identifier>
::= the <IDENTIFIER> of a module output or inout terminal.
<path_delay_value>
::= <path_delay_expression>
||= ( <path_delay_expression>, <path_delay_expression> )
||= ( <path_delay_expression>, <path_delay_expression>,
<path_delay_expression>)
||= ( <path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression> )
||= ( <path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression>,
<path_delay_expression>, <path_delay_expression> )
<path_delay_expression>
::= <mintypmax_expression>
<system_timing_check>
::= $setup( <timing_check_event>, <timing_check_event>,
<timing_check_limit>
<,<notify_register>>? ) ;
||= $hold( <timing_check_event>, <timing_check_event>,
<timing_check_limit>
<,<notify_register>>? ) ;
||= $period( <controlled_timing_check_event>, <timing_check_limit>
<,<notify_register>>? ) ;
||= $width( <controlled_timing_check_event>, <timing_check_limit>
<,<constant_expression>,<notify_register>>? ) ;
||= $skew( <timing_check_event>, <timing_check_event>,
<timing_check_limit>
<,<notify_register>>? ) ;
||= $recovery( <controlled_timing_check_event>,
<timing_check_event>,
<timing_check_limit> <,<notify_register>>? ) ;
||= $setuphold( <timing_check_event>, <timing_check_event>,
<timing_check_limit>, <timing_check_limit> <,<notify_register>>? ) ;
<timing_check_event>
::= <timing_check_event_control>? <specify_terminal_descriptor>
<&&& <timing_check_condition>>?
<specify_terminal_descriptor>
::= <specify_input_terminal_descriptor>
||=<specify_output_terminal_descriptor>
<controlled_timing_check_event>
::= <timing_check_event_control> <specify_terminal_descriptor>
<&&& <timing_check_condition>>?
<timing_check_event_control>
::= posedge
||= negedge
||= <edge_control_specifier>
<edge_control_specifier>
::= edge [ <edge_descriptor><,<edge_descriptor>>*]
<edge_descriptor>
::= 01
||= 10
||= 0x
||= x1
||= 1x
||= x0
<timing_check_condition>
::= <scalar_timing_check_condition>
||= ( <scalar_timing_check_condition> )
<scalar_timing_check_condition>
::= <scalar_expression>
||= ~<scalar_expression>
||= <scalar_expression> == <scalar_constant>
||= <scalar_expression> === <scalar_constant>
||= <scalar_expression> != <scalar_constant>
||= <scalar_expression> !== <scalar_constant>
<scalar_expression>
1ビットのネットまたは、vector netのビットセレクト.
<timing_check_limit>
::= <expression>
<scalar_constant>
::= 1'b0
||= 1'b1
||= 1'B0
||= 1'B1
||= 'b0
||= 'b1
||= 'B0
||= 'B1
||= 1
||= 0
<notify_register>
::= <identifier>
<level_sensitive_path_declaration>
::= if (<conditional_port_expression>)
(<specify_input_terminal_descriptor> <polarity_operator>? =>
<specify_output_terminal_descriptor>) = <path_delay_value>;
||= if (<conditional_port_expression>)
(<list_of_path_inputs> <polarity_operator>? *>
<list_of_path_outputs>) = <path_delay_value>;
(Note: 次のシンボルは、トークン)
*> =>
<conditional_port_expression>
::= <port_reference>
||= <UNARY_OPERATOR><port_reference>
||= <port_reference><BINARY_OPERATOR><port_reference>
<polarity_operator>
::= +
||= -
<edge_sensitive_path_declaration>
::= <if (<expression>)>? (<edge_identifier>?
<specify_input_terminal_descriptor> =>
(<specify_output_terminal_descriptor> <polarity_operator>?
: <data_source_expression>)) = <path_delay_value>;
||= <if (<expression>)>? (<edge_identifier>?
<specify_input_terminal_descriptor> *>
(<list_of_path_outputs> <polarity_operator>?
: <data_source_expression>)) =<path_delay_value>;
<data_source_expression>
<edge_identifier>
::= posedge
||= negedge
<sdpd>
::=if(<sdpd_conditional_expression>)<path_description>=<path_delay_value>;
<sdpd_conditional_expresssion>
::=<expression><BINARY_OPERATOR><expression>
||=<UNARY_OPERATOR><expression>
<lvalue> ::= <identifier> ||= <identifier> [ <expression> ] ||= <identifier> [ <constant_expression> : <constant_expression> ] ||= <concatenation> <constant_expression> ::=<expression> <mintypmax_expression> ::= <expression> ||= <expression> : <expression> : <expression> <expression> ::= <primary> ||= <UNARY_OPERATOR> <primary> ||= <expression> <BINARY_OPERATOR> <expression> ||= <expression> <QUESTION_MARK> <expression> : <expression> ||= <STRING> <UNARY_OPERATOR> tokens: + - ! ~ & ~& | ^| ^ ~^ <BINARY_OPERATOR> tokens: + - * / % == != === !== && || < <= > >= & | ^ ^~ >> << <QUESTION_MARK> ? <STRING> " " で囲まれた一行のテキスト <primary> ::= <number> ||= <identifier> ||= <identifier> [ <expression> ] ||= <identifier> [ <constant_expression> : <constant_expression> ] ||= <concatenation> ||= <multiple_concatenation> ||= <function_call> ||= ( <mintypmax_expression> ) <number> ::= <DECIMAL_NUMBER> ||= <UNSIGNED_NUMBER>? <BASE> <UNSIGNED_NUMBER> ||= <DECIMAL_NUMBER>.<UNSIGNED_NUMBER> ||= <DECIMAL_NUMBER><.<UNSIGNED_NUMBER>>? E<DECIMAL_NUMBER> ||= <DECIMAL_NUMBER><.<UNSIGNED_NUMBER>>? e<DECIMAL_NUMBER> <DECIMAL_NUMBER> ::= 0123456789_の集合体 +-が前にあってもよい UNSIGNED_NUMBER> ::= 0123456789_の集合体 <NUMBER> decimal, hexadecimal, octal または binary 表現が可能。+または -で始まってもよい。 <BASE> は d, h, o, or bのいずれかで、10進、16進、8進、2進に対応する。数字はベースに対応した次の文字セット 0123456789abcdefABCDEFxXzZ? <BASE> tokens: 'b 'B 'o 'O 'd 'D 'h 'H <concatenation> ::= { <expression> <,<expression>>* } <multiple_concatenation> ::= { <expression> { <expression> <,<expression>>* } } <function_call> ::= <name_of_function> ( <expression> <,<expression>>* ) ||= <name_of_system_function> ( <expression> <,<expression>>* ) ||= <name_of_system_function> <name_of_function> ::= <identifier> <name_of_system_function> ::= $<SYSTEM_IDENTIFIER>
<comment>
::= <short_comment>
||= <long_comment>
<short_comment>
::= // <comment_text> <END-OF-LINE>
<long_comment>
::=/* <comment_text> */
<comment_text>
::= コメントテキストは0以上のASCII characters
<identifier>
::= <IDENTIFIER><.<IDENTIFIER>>*
(ピリオドは、空白スペースの前後にあってはならない。)
<IDENTIFIER>
識別子は、文字、数字、 ($), アンダースコア (_)の連続文字列。 ただし始まりは文字かアンダースコアであること。大文字と小文字は違った識別子と解釈される。
エスケープ文字列は、印刷可能なASCIIキャラクタを含むことが出来る。
<delay>
::= # <number>
||= # <identifier>
||= # ( <mintypmax_expression> <,<mintypmax_expression>>?
<,<mintypmax_expression>>?)
<delay_control>
::= # <number>
||= # <identifier>
||= # ( <mintypmax_expression> )
<event_control>
::= @ <identifier>
||= @ ( <event_expression> )
<event_expression>
::= <expression>
||= posedge <scalar_event_expression>
||= negedge <scalar_event_expression>
||= <event_expression> or <event_expression>
<scalar_event_expression>
1ビットのEVENT表現