YACC_XILINX2 Project Status | |||
Project File: | yacc_xilinx2.ise | Current State: | Placed and Routed |
Module Name: | hardware_top |
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No Errors |
Target Device: | xc3s1500-5fg320 |
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439 Warnings |
Product Version: | ISE 9.1.02i |
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? 5 8 10:21:04 2007 |
YACC_XILINX2 Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 961 | 26,624 | 3% | |
Number of 4 input LUTs | 4,308 | 26,624 | 16% | |
Logic Distribution | ||||
Number of occupied Slices | 2,539 | 13,312 | 19% | |
Number of Slices containing only related logic | 2,539 | 2,539 | 100% | |
Number of Slices containing unrelated logic | 0 | 2,539 | 0% | |
Total Number of 4 input LUTs | 4,762 | 26,624 | 17% | |
Number used as logic | 4,308 | |||
Number used as a route-thru | 67 | |||
Number used for Dual Port RAMs | 384 | |||
Number used as Shift registers | 3 | |||
Number of bonded IOBs | 216 | 221 | 97% | |
IOB Flip Flops | 7 | |||
Number of Block RAMs | 20 | 32 | 62% | |
Number of MULT18X18s | 2 | 32 | 6% | |
Number of GCLKs | 1 | 8 | 12% | |
Total equivalent gate count for design | 1,382,026 | |||
Additional JTAG gate count for IOBs | 10,368 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | ? 5 8 10:06:16 2007 | 0 | 437 Warnings | 35 Infos |
Translation Report | Current | ? 5 8 10:06:39 2007 | 0 | 0 | 0 |
Map Report | Current | ? 5 8 10:07:22 2007 | 0 | 2 Warnings | 3 Infos |
Place and Route Report | Current | ? 5 8 10:19:56 2007 | 0 | 0 | 2 Infos |
Static Timing Report | Current | ? 5 8 10:21:03 2007 | 0 | 0 | 3 Infos |
Bitgen Report |