| YACC_XILINX2 Project Status | |||
| Project File: | yacc_xilinx2.ise | Current State: | Placed and Routed |
| Module Name: | cache_module |
|
No Errors |
| Target Device: | xc3s1500-5fg320 |
|
3 Warnings |
| Product Version: | ISE 9.1.02i |
|
? 3 27 12:29:11 2007 |
| YACC_XILINX2 Partition Summary | |||
| No partition information was found. |
| Device Utilization Summary | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Flip Flops | 98 | 26,624 | 1% | |
| Number of 4 input LUTs | 494 | 26,624 | 1% | |
| Logic Distribution | ||||
| Number of occupied Slices | 254 | 13,312 | 1% | |
| Number of Slices containing only related logic | 254 | 254 | 100% | |
| Number of Slices containing unrelated logic | 0 | 254 | 0% | |
| Total Number of 4 input LUTs | 494 | 26,624 | 1% | |
| Number of bonded IOBs | 210 | 221 | 95% | |
| IOB Flip Flops | 37 | |||
| Number of Block RAMs | 11 | 32 | 34% | |
| Number of GCLKs | 1 | 8 | 12% | |
| Total equivalent gate count for design | 725,141 | |||
| Additional JTAG gate count for IOBs | 10,080 | |||
| Performance Summary | |||
| Final Timing Score: | 0 | Pinout Data: | Pinout Report |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
| Timing Constraints: | All Constraints Met | ||
| Detailed Reports | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos |
| Synthesis Report | Current | ? 3 27 12:27:23 2007 | 0 | 3 Warnings | 16 Infos |
| Translation Report | Current | ? 3 27 12:27:38 2007 | 0 | 0 | 0 |
| Map Report | Current | ? 3 27 12:27:54 2007 | 0 | 0 | 3 Infos |
| Place and Route Report | Current | ? 3 27 12:28:58 2007 | 0 | 0 | 2 Infos |
| Static Timing Report | Current | ? 3 27 12:29:10 2007 | 0 | 0 | 3 Infos |
| Bitgen Report | |||||