９．全体接続
いままでのモジュールを接続します。
このモジュールは論理合成TOPとなります。多くの信号接続で出やすいバグは、信号の名前が違うものです。たとえば、[1:0]ram_access_modeのところram_acess_mode
とやってしまうと1ビットのWIRE信号として解釈されFloatingの信号に接続することになり構文エラーにもならずつまらないところでDebug時間を食ってしまいことがあります。Veritakでは、明示的にWire宣言、Reg宣言されているものは、Scope Viewで色分け表示しています。暗黙Wire信号は色が付かないのですぐわかります。ハード記述を完成させたらScopeViewを一度見ておくといいでしょう。
RTLデバッグでは、外に出力信号をださなくともいいのですが、論理合成の際、賢い合成器は最適化により空の回路を生成してしまうので、回路動作で必須の信号を外にだしてこれを防ぎます。
//May.31.2004
`include "define.h"
module H8(clock,sync_reset,MOUT,int_req2,int_req2_ack);
input clock;
input sync_reset;
output [31:0] MOUT;
input int_req2;
output int_req2_ack;
reg [7:0] int_vector=8'h20;//Interim May.31.2004
//ram_module
wire ram_write;
wire [1:0] ram_access_mode;
wire [1:0] paddress_sel;
wire data_address_latch;
wire ram_data_in_sel;
//ea_unit
wire [3:0] ea_left_sel;
wire [2:0] ea_right_sel;
wire [3:0] ea_reg_address;//Jun.3.2004
wire [2:0] next_pc_offset;
//alu
wire [1:0] alu_left_sel;
wire [3:0] alu_right_sel;
wire [4:0] ope;
wire imm_sel;
wire v_clear,h_latch,n_latch,z_latch,v_latch,c_latch, ccr_all_write;
wire [1:0] ccr_input_sel;
wire [1:0] bus_state;
wire [1:0] alu_access_mode;
//reg_file
wire [1:0] left_address_sel, right_address_sel;
wire [2:0] write_address_sel;
wire [1:0] reg_file_access_mode;
wire reg_write;
wire insel;
wire [63:0] irword;
wire [31:0] MOUT;
wire [31:0] ALU_OUT;
wire [23:0] EA,pc_reg;
wire [31:0] RO_left,RO_right,left_address_out;
wire [31:0] z_bus;
wire [7:0] CCR;
wire BCC_jmp;
wire [7:0] IR1=irword[23+32:16+32];
wire [7:0] IR3=irword[23+32-16:16+32-16];
wire i_bit;
wire [7:0] state;
wire stop_state;
wire [31:0] reg_out_for_mul_div;
assign ea_reg_address=ea_left_sel==`PC_SEL ? IR1[3:0] : //Jun.3.2004
ea_left_sel==`ABS8_SEL ? IR3[3:0] : //Jun.3.2004
ea_left_sel==`IR1H_SEL_EA? IR1[7:4] :IR3[7:4];//May.31.2004
assign reg_out_for_mul_div=alu_access_mode == `LONG_ACCESS ? left_address_out :
alu_access_mode == `WORD_ACCESS ? ( ea_reg_address[3] ==1'b1 ? {16'h0000,left_address_out[31:16]} : {16'h0000,left_address_out[15:0]} ) :
ea_reg_address[3] ==1'b0 ? {24'h00_0000,left_address_out[15:8]} : {24'h00_0000,left_address_out[7:0]} ; //Note: register field mapping R0H =>0000, R0L=>1000
// always @(negedge clock) temp <=mul_div_dest_reg_out;
decoder d1(clock,sync_reset, ram_write,ram_access_mode,data_address_latch,
ram_data_in_sel,irword, ea_left_sel, ea_right_sel,next_pc_offset,
alu_left_sel,alu_right_sel,ope,alu_access_mode,imm_sel,v_clear,h_latch,n_latch,z_latch,v_latch,c_latch,
ccr_all_write,bus_state,ccr_input_sel,paddress_sel,
left_address_sel, right_address_sel,write_address_sel,reg_file_access_mode,
reg_write, insel,int_req2,int_req2_ack,i_bit,stop_state,state);
/* decoder decoder1(clock,sync_reset, ram_write,ram_access_mode,data_address_latch,
ram_data_in_sel,irword, ea_left_sel, ea_right_sel,next_pc_offset,
alu_left_sel,alu_right_sel,ope,alu_access_mode,imm_sel,v_clear,h_latch,n_latch,z_latch,v_latch,c_latch,
ccr_all_write,bus_state,ccr_input_sel,paddress_sel,
left_address_sel, right_address_sel,write_address_sel,reg_file_access_mode,
reg_write, insel,int_req2,int_req2_ack,i_bit,state,stop_state,state);
*/
h8_ram_module ram_module (.clock(clock),.sync_reset(sync_reset),.ram_write(ram_write),
.paddress_sel(paddress_sel),.EA(EA),.data_address_latch(data_address_latch),
.bcc_ea_sel(BCC_jmp),.IR(irword),.MOUT(MOUT),.access_mode(ram_access_mode),
.ALU_OUT(z_bus),.ram_data_in_sel(ram_data_in_sel),.pc_reg(pc_reg),.next_pc_offset(next_pc_offset),.ea_left_sel(ea_left_sel),.CCR(CCR),.bus_state(bus_state));
ALU alu(.clock(clock),.sync_reset(sync_reset),.alu_left_sel(alu_left_sel),
.alu_right_sel(alu_right_sel),.ope(ope),.imm_sel(imm_sel),.v_clear(v_clear),
.h_latch(h_latch),.n_latch(n_latch),.z_latch(z_latch),.v_latch(v_latch),.c_latch(c_latch),
.ccr_all_write(ccr_all_write),.access_mode(alu_access_mode),
.RO_left(RO_left),.RO_right(RO_right),.irword(irword),.MOUT(MOUT),
.bus_state(bus_state),.ccr_input_sel(ccr_input_sel),.z_bus(z_bus),.CCR(CCR),.BCC_jmp(BCC_jmp),.i_bit(i_bit),.stop_state(stop_state),.state(state),
.mul_div_dest_reg(reg_out_for_mul_div),.mul_div_address3(ea_reg_address[3]));//Jun.3.2004
ea_unit EA_Unit(.clock(clock),.sync_reset(sync_reset),.EA(EA),.irword(irword),.ea_left_sel(ea_left_sel),
.ea_right_sel(ea_right_sel),
.RO_left(left_address_out),.alu_out(z_bus),.MOUT(MOUT),.pc_reg(pc_reg),.next_pc_offset(next_pc_offset),.int_vector(int_vector));
reg_file RegFile(.clock(clock),.sync_reset(sync_reset),.irhword(irword[63:32]),
.left_address_sel(left_address_sel),.right_address_sel(right_address_sel),
.write_address_sel(write_address_sel), .access_mode(reg_file_access_mode),
.reg_write(reg_write),.alu_out(z_bus),.ea(EA),
.reg_left_out(RO_left), .reg_right_out(RO_right),.insel(insel),.left_address_out(left_address_out),.ea_reg_address(ea_reg_address[2:0]));
endmodule
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