5. デコーダ
デコーダは、RAMモジュールのインストラクションレジスタ(64ビット）と、ステートを入力とする巨大な組み合わせ回路になります。サブセット仕様と言えど、アドレシングモードも含むとマイクロコードは、３００位あります。あまりに命令が多いので書いていて厭になります。
（16ビットから32ビットへの拡張を担当した人に同情します。）
BCD演算とLONGの24ビット相対アドレシングは、サブセット仕様ということで省いています。
この巨大なデコードと実行を１ステートでやってしまうというのが、当初のプランです。遅延対策は後で考えることにしてとりあえず進みましょう。
アーキテクチャでもExcelは書いたのですが、今回は、実際にVerilog上で記述するために、Verilog形式のフォーマットに直す必要があります。慣れないExcelでこの作業をやってみました。なお、Excelでマイクロコードを書く方法は、米国で仕事をした際、エンジニアがやっていた方法を真似たものです。言わばマイクロコードアセンブラです。
（余談ですが、Matlabや、Mathmatica,Verilog,Design Compiler等、先進的なソフトは全て米国人によるものですね。）
ほぼデバッグが終わったEXCELコードです。
下記はVerilogに直したデコーダになります。筆者が今まで書いたデコーダのなかで一番でかいです。考えてみるとH8300Hは、（演算ビット幅で考える）と32ビットマイコンです。H8の下位機種は、16ビットなので、そんなに複雑なことはないのですが、BYTE,WORD,LONGがあるために命令数が多くなりデコーダにしわ寄せが来てしまいました。16ビットCPUの方がデコーダは簡易なので速度的に上げやすいと思います。
（余談ですが、昔32ビットスーパミニコンなんてのがありました。当時は、16ビットのCPUでラック入りのミニコンを作っていたのですが、レジスタ間演算が300ns（300psではありません。）で堂々とカタログスペックに載っていました。）
繰り返しますがデコーダは組み合わせ回路です。下で、bus_stateは、RESET,割り込み、実行状態等の大局的ステート、irwordは、64ビットインストラクションレジスタ、STは実行ステートです。これを入力として一意に制御信号（マイクロコード52ビット）は決まります。デコーダモジュールからのoutput信号は、各モジュールに行き状態を制御することになります。マイクロコードをそのままマシンコードにすればVLIW
CPU？になります。
割り込みを含む全ての実行ステート数は最大でも５ステートで、メモリReadを含まない命令は２ステート（Fetch,Decode/Excute)で実行します。オリジナルでは、最大で１２ステート（同じ命令で比較）かかる命令もあります。FPGAの任意バス幅が効いています。
なお、割り込みは、固定Vectorです。
コーディングではtaskを使って書いてみました。Quartasでは問題なく論理合成できました。少しでも、デコーダの負担を軽くするために、8ステート１ホットコード（ST)にしてみました。（乗除算命令を載せた時を考えて少し多めにしておきました。）case文では、？（ドントケア）は使えません。casezもしくはcasexを使います。これで論理合成器に ”ここは、簡単にデコードできるよ” と教えてあげましょう。
`include "define.h"
//Jun.2.2004 add stop_state
module decoder(clock,sync_reset, ram_write,ram_access_mode,data_address_latch,
ram_data_in_sel,irword, ea_left_sel, ea_right_sel,next_pc_offset,
alu_left_sel,alu_right_sel,ope,alu_access_mode,imm_sel,v_clear,h_latch,n_latch,z_latch,v_latch,c_latch,
ccr_all_write,bus_state,ccr_input_sel,paddress_sel,
left_address_sel, right_address_sel,write_address_sel,reg_file_access_mode,
reg_write, insel,int_req2,int_req2_ack,i_bit,stop_state,ST);
input clock,sync_reset;
input [63:0] irword;
//ram_module
output ram_write;
output [1:0] ram_access_mode;
output [1:0] paddress_sel;
output data_address_latch;
output ram_data_in_sel;
//ea_unit
output [3:0] ea_left_sel;
output [2:0] ea_right_sel;
output [2:0] next_pc_offset;
//alu
output [1:0] alu_left_sel;
output [3:0] alu_right_sel;
output [4:0] ope;
output imm_sel;
output v_clear,h_latch,n_latch,z_latch,v_latch,c_latch, ccr_all_write;
output [1:0] ccr_input_sel;
output [1:0] bus_state;
output [1:0] alu_access_mode;
//reg_file
output [1:0] left_address_sel, right_address_sel;
output [2:0] write_address_sel;
output [1:0] reg_file_access_mode;
output reg_write;
output insel;
input int_req2;
output int_req2_ack;
input i_bit;
input stop_state;
output [7:0] ST;
//registers
reg [7:0] ST;//state
reg [1:0] bus_state;
reg int_latch;
reg int_req2_ack;
//combinational logics
//alu
reg [1:0] alu_left_sel;
reg [3:0] alu_right_sel;
reg [4:0] ope;
reg imm_sel;
reg [1:0] alu_access_mode;
reg v_clear,h_latch,n_latch,z_latch,v_latch,c_latch, ccr_all_write;
reg [1:0] ccr_input_sel;
//reg_file
reg [1:0] left_address_sel, right_address_sel;
reg [2:0] write_address_sel;
reg [1:0] reg_file_access_mode;
reg reg_write;
reg insel;
//ea_unit
reg [3:0] ea_left_sel;
reg [2:0] ea_right_sel;
reg [2:0] next_pc_offset;
//ram_module
reg ram_write;
reg [1:0] ram_access_mode;
reg [1:0] paddress_sel;
reg data_address_latch;
reg ram_data_in_sel;
//state control
reg end_state;
task c_vect;
input [51:0] vector;
{
end_state, // 1
//alu
alu_left_sel, //2
alu_right_sel, //4
ope, //5
alu_access_mode, //2
imm_sel, //1
v_clear,h_latch,n_latch,z_latch,v_latch,c_latch, ccr_all_write,//7
ccr_input_sel, //2
//reg_file
insel, //1
left_address_sel, right_address_sel,//4
write_address_sel, //3
reg_write, //1
reg_file_access_mode,//2
//ram_module
ram_data_in_sel , //1
ram_write, //1
ram_access_mode, //2
paddress_sel, //2
data_address_latch, //1
//ea_unit
ea_left_sel, //4
ea_right_sel, //3
next_pc_offset, //3
} = vector ; //
endtask
always @(bus_state or irword or ST ) begin
//e le righ ope m i vhnzvcw ci i le ri wad w m i w m pa l left rig off
if (bus_state==2'b00) c_vect(52'b0_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);// ar=ar,pc=pc
else if (bus_state==2'b01) // reset sequence
casex (ST) //e le righ ope m i vhnzvcw ci i le ri wad w m i w m pa l left rig off
8'b0000_0000: // c_vect(52'b0_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000); //
c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_???1: // c_vect(52'b1_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_10_10_0_0000_000_000); //
c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_10_1_0000_000_000);
// 8'b????_??1?: c_vect(52'b0_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
// 8'b????_?1??: c_vect(52'b0_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
default: ;
endcase
else if (bus_state==2'b10) // Int Cycle #of cycles may be less than H8
casex(ST)
8'b0000000000:c_vect( 52'b_0_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_0000_000_001);
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_00_0_1110_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_1_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_01_0_1010_000_000);
default: $stop;
endcase
else if (ST==8'h00) // Fetch Cycle
c_vect(52'b0_00_0000_00000_00_0_0000000_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
else begin
casex(irword[63:60])
4'b1111: casex(ST) // MOV.B. #x:8,Rd
8'b????_???1: c_vect( 52'b_1_01_0000_00001_00_0_1_0_1_1_0_0_0_00_0_00_00_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0110:
casex(irword[59:56])
4'b0100: // OR.W Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00111_01_0_1_0_1_1_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0101: // XOR.W Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01000_01_0_1_0_1_1_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0110: // AND.W Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00110_01_0_1_0_1_1_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1000: // MOV.B. @Rs,Rd
casex (irword[55])
1'b0 : // 6 8 0rsrd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1: // MOV.B Rs,@Rd 6 8 1rdrs
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_01_00_000_0_00_0_1_00_00_0_0110_000_001);
default: $stop;
endcase // ST
endcase // IR[7]
4'b1001: // MOV.W. @Rs,Rd
casex (irword[55])
1'b0 : // 6 9 0rsrd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_01_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1: // MOV.W Rs,@Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_01_00_000_0_01_0_1_01_00_0_0110_000_001);
default: $stop;
endcase // ST
endcase // IR[7]
4'b1010:
casex (irword[55:52])
4'b0000:// MOV.B. @aa:16,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0010_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_010);
default:$stop;
endcase // ST
4'b0010:// MOV.B. @aa:24,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0100_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_011);
default:$stop;
endcase // ST
4'b1000: // MOV.B. Rs,@aa:16
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0010_000_010);
default:$stop;
endcase // ST
4'b1010: // MOV.B. Rs,@aa:24
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0100_000_011);
default:$stop;
endcase // ST
default: $stop;
endcase // IR_BYTE[7]
4'b1011:
casex (irword[55:52])
4'b0000:// MOV.W. @aa:16 ,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_01_00_0_0010_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_010);
default: $stop;
endcase // ST
4'b0010: // MOV.W. @aa:24,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_01_00_0_0100_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_011);
default:$stop;
endcase // ST
4'b1000:// MOV.W. Rs,@aa:16
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_0_01_0_1_01_00_0_0010_000_010);
default: $stop;
endcase // ST
4'b1010: // MOV.W. Rs,@aa:24
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_0_01_0_1_01_00_0_0100_000_011);
default:$stop;
endcase // ST
default: $stop;
endcase // IR_BYTE[7]
4'b1100:
casex (irword[55])
1'b0: // MOV.B @Ers+,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_0_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_000);
8'b????_1???: c_vect( 52'b_1_00_0010_00010_10_0_0_0_0_0_0_0_0_00_0_01_00_101_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1: // MOV.B Rs,@-ERd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_1_0_1_1_0_0_0_00_1_01_00_101_1_10_0_0_00_00_0_0110_110_000);
8'b????_??1?: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_01_00_000_0_00_0_1_00_00_0_0110_000_001);
default: $stop;
endcase // ST
endcase // IR_BYTE[7]
4'b1101:
casex (irword[55])
1'b0: // MOV.W @Rs++,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_01_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_0_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_000);
8'b????_1???: c_vect( 52'b_1_00_0011_00010_10_0_0_0_0_0_0_0_0_00_0_01_00_101_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1: // MOV.W. Rs,--@ERd 6 D 1rd rs
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_01_0_1_0_1_1_0_0_0_00_1_01_00_101_1_10_0_0_01_00_0_0110_101_000);
8'b????_??1?: c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_01_00_000_0_01_0_1_01_00_0_0110_000_001);
default: $stop;
endcase // ST
endcase // IR_BYTE[7]
4'b1110:
casex (irword[55])
1'b0: //MOV.B @(d:16,Ers),Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_010_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_010);
default: $stop;
endcase // ST
1'b1: // MOV.B Rs,@(d;16:ERd)
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_01_00_000_0_00_0_1_00_00_0_0110_010_010);
default: $stop;
endcase // ST
endcase // IR_BYTE[7]
4'b1111:
casex (irword[55])
1'b0: // MOV.W. @(d:16,ERs),Rd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_01_00_0_0110_010_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_010);
default: $stop;
endcase // ST
1'b1: // Mov.W. Rs,@(d:16,ERd)
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_01_00_000_0_01_0_1_01_00_0_0110_010_010);
default: $stop;
endcase // ST
endcase // IR_BYTE[7]
default: $stop;
endcase // IR[11:8]
4'b0111: casex(irword[59:56])
4'b0000: // BITSET.B #xx:3 Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10100_00_1_0_0_0_0_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001: // BITNOT.B #xx:3 Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10101_00_1_0_0_0_0_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0010: // BITCLR.B #xx:3 Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10011_00_1_0_0_0_0_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011: // BTST.B #xx:3 Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10110_00_1_0_0_0_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
endcase // ST
4'b1000:
casex(irword[47:36])
12'h6A2:
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_111_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_100);
endcase//
12'h6aa:
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_01_00_000_0_00_0_1_00_00_0_0110_111_100);
endcase//
12'h6b2:
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_01_00_0_0110_111_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_1000_00000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_01_00_0_0000_000_100);
endcase//
12'h6ba:
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00000_01_0_1_0_1_1_0_0_0_00_0_01_00_000_0_01_0_1_01_00_0_0110_111_100);
endcase//
endcase //ST
4'b1001:
casex(irword[55:52])
4'b0000:// MOV.W. #xx:16,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_10_0000_00001_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase // ST
4'b0001:// ADD.W.#xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_00010_01_0_0_1_1_1_1_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase // ST
4'b0010:// CMP.W #xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_00011_01_0_0_1_1_1_1_1_0_00_0_00_00_000_0_01_0_0_00_00_0_0000_000_010);
endcase // ST
4'b0011:// SUB.W.#xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_00011_01_0_0_1_1_1_1_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase // ST
4'b0100://OR.W.#xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_00111_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase
4'b0101://XOR.W.#xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_01000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase
4'b0110://AND.W.#xx:16,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_10_0000_00110_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_010);
endcase
// default:$stop;
endcase
4'b1010:
casex(irword[55:52])
4'b0000: //MOV.L ##x:32,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_00001_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
4'b0001: //ADD.L ##x:32,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_00010_10_0_0_1_1_1_1_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
4'b0010: //CMP.L ##x:32,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_11_0000_00011_10_0_0_1_1_1_1_1_0_00_0_00_00_000_0_10_0_0_00_00_0_0000_000_011);
endcase
4'b0011: //SUB.L ##x:32,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_00011_10_0_0_1_1_1_1_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
4'b0100: //OR.L #xx:32,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_00111_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
4'b0101: //XOR.L #xx:32,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_01000_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
4'b0110: //AND.L #xx:32,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_11_0000_00110_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_011);
endcase
default: $stop;
endcase
4'b1100:
casex(irword[47:40])
8'h73:// BTST #xx:3, @Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_1_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10110_00_0_0_0_0_1_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0110_000_010);
default: $stop;
endcase
default:$stop;
endcase
4'b1101:
casex(irword[47:40])
8'h70:// BSET #xx:3, @Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10100_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0110_000_010);
default: $stop;
endcase
8'h71:// BNOT #xx:3, @Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10101_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0110_000_010);
default: $stop;
endcase
8'h72:// BCLR #xx:3, @Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10011_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0110_000_010);
default: $stop;
endcase
default:$stop;
endcase
4'b1101:
casex(irword[47:40])
8'h73:// BTST #xx:3,@aa:8
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10110_00_0_0_0_0_1_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0110_000_010);
default: $stop;
endcase
default: $stop;
endcase
4'b1111:
casex(irword[47:40])
8'h70:// BSET #xx:3, @aa:8
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10100_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0001_000_010);
default: $stop;
endcase
8'h71:// BNOT #xx:3, @aa:8
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10101_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0001_000_010);
default: $stop;
endcase
8'h72:// BCLR #xx:3, @aa:8
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_10011_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0001_000_010);
default: $stop;
endcase
default:$stop;
endcase
default:$stop;
endcase // IR[11:8]
4'b1000: // ADD.B #xx:8,Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_01_0000_00010_00_0_0_1_1_1_1_1_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
endcase // ST
4'b1001: // ADDX.B #xx:8,Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_01_0000_00100_00_0_0_1_1_1_1_1_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1010: // CMP.B ##xx:8,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_01_0000_00011_00_0_0_1_1_1_1_1_0_00_0_00_01_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011: //SUBX #xx:8,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_01_0000_00101_00_0_0_1_1_1_1_1_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1101: // XOR #xx:8, Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_01_0000_01000_00_0_1_0_1_1_0_0_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1100: // OR #xx:8, Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_01_0000_00111_00_0_1_0_1_1_0_0_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1110: // AND #xx:8, Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_01_0000_00110_00_0_1_0_1_1_0_0_0_00_0_00_01_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0000: casex(irword[59:56])
4'b0000:
casex(irword[55:48])
8'h00:// NOP
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
// default:$stop;
endcase
4'b0001:
casex(irword[55:48])
8'h00://
casex(irword[47:40])
8'h69:
if(!irword[39])//// MOV.L @ERs,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_10_00_000_0_00_0_0_10_00_0_0111_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_10_0_1_0_1_1_0_0_0_00_0_00_00_010_1_10_0_0_10_00_0_0000_000_010);
endcase // ST
else//MOV.L Rs,@(ERd)
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_10_0_1_0_1_1_0_0_0_00_0_10_10_000_0_10_0_1_10_00_0_0111_000_010);
endcase // ST
8'h6B:
case (irword[39:36])
4'b0000://MOV.L @aa16,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_00_0_0011_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_1000_00000_10_0_1_0_1_1_0_0_0_00_0_00_00_010_1_10_0_0_10_00_0_0000_000_011);
endcase // ST
4'b0010://MOV.L @aa24,ERd
casex(ST)//
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_00_0_0101_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_1000_00000_10_0_1_0_1_1_0_0_0_00_0_00_00_010_1_10_0_0_10_00_0_0000_000_100);
endcase // ST
4'b1000://MOV.L ERs,@aa:16
casex(ST)//
8'b????_???1:c_vect( 52'b_1_00_0000_00000_10_0_1_0_1_1_0_0_0_00_0_00_10_000_0_10_0_1_10_00_0_0011_000_011);
endcase // ST
4'b1010:
casex(ST)//MOV.L ERs,@aa:24
8'b????_???1:c_vect( 52'b_1_00_0000_00000_10_0_1_0_1_1_0_0_0_00_0_00_10_000_0_10_0_1_10_00_0_0101_000_100);
endcase // ST
default: $stop;
endcase
8'h6D:
if(!irword[39])//MOV.L @Ers+,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_10_00_000_0_00_0_0_10_00_0_0111_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_0_00_1000_00000_10_0_1_0_1_1_0_0_0_00_0_00_00_010_1_10_0_0_10_00_0_0000_000_000);
8'b????_1???:c_vect( 52'b_1_00_0100_00010_10_0_0_0_0_0_0_0_0_00_0_10_00_011_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
else//
casex(ST)//MOV.L Rs,@-ERd
8'b????_???1:c_vect( 52'b_1_00_0000_00000_10_0_1_0_1_1_0_0_0_00_1_10_10_011_1_10_0_1_10_00_0_0111_100_010);
endcase // ST
8'h6F:
if(!irword[39])//// MOV.L @(d:16,ERs),ERd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_10_00_000_0_00_0_0_10_00_0_0111_011_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_10_0_1_0_1_1_0_0_0_00_0_00_00_010_1_10_0_0_10_00_0_0000_000_011);
endcase
else
casex(ST) //MOV.L Rs,@(d;16:ERd)
8'b????_???1:c_vect( 52'b_1_00_0000_00000_10_0_1_0_1_1_0_0_0_00_0_10_10_000_0_10_0_1_10_00_0_0111_011_011);
endcase // ST
// default: $stop;
endcase
8'hc0:
casex(irword[47:40])
8'h50:////MULXS.B Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_10_10_010_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?:c_vect( 52'b_1_00_1010_00000_01_0_0_0_1_1_0_0_0_00_0_10_10_010_1_01_0_0_00_00_0_0000_000_010);
endcase // ST
8'h52://MULXS.W Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_10_10_010_0_01_0_0_00_00_0_0001_000_000);
8'b????_??1?:c_vect( 52'b_1_00_1010_00000_10_0_0_0_1_1_0_0_0_00_0_10_10_010_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
// default: $stop;
endcase
8'hd0: //DIVXS.B Rs,Erd
casex(irword[47:40])
8'h51://DIVXS.B Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00001_00_0_0_0_0_1_0_0_0_00_0_10_10_010_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_10_10_010_0_00_0_0_00_00_0_0001_000_000);
8'b????_?1??:c_vect( 52'b_0_00_1010_00001_01_0_0_0_0_0_0_0_0_00_0_10_10_010_0_01_0_0_00_00_0_0000_000_000);
8'b????_1???:c_vect( 52'b_1_00_1010_00000_01_0_0_0_0_0_0_0_0_00_0_10_10_010_1_01_0_0_00_00_0_0000_000_010);
endcase // ST
8'h53://DIVXS.W Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00001_01_0_0_0_0_1_0_0_0_00_0_10_10_010_0_01_0_0_00_00_0_0001_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_10_0_0_0_0_0_0_0_0_00_0_10_10_010_0_01_0_0_00_00_0_0001_000_000);
8'b????_?1??:c_vect( 52'b_0_00_1010_00001_10_0_0_0_0_0_0_0_0_00_0_10_10_010_0_10_0_0_00_00_0_0000_000_000);
8'b????_1???:c_vect( 52'b_1_00_1010_00000_10_0_0_0_0_0_0_0_0_00_0_10_10_010_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
// default: $stop;
endcase
8'hf0://
casex(irword[47:40])
8'h64:// OR.L ERs,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00111_10_0_1_0_1_1_0_0_0_00_0_10_10_010_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
8'h65:// XOR.L ERs,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01000_10_0_1_0_1_1_0_0_0_00_0_10_10_010_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
8'h66:// AND.L ERs,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00110_10_0_1_0_1_1_0_0_0_00_0_10_10_010_1_10_0_0_00_00_0_0000_000_010);
endcase // ST
// default: $stop;
endcase
8'h40://
casex(irword[47:40])
8'h69:
if (!irword[39])// LDC @ERs,CCR
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_010);
endcase // ST
else
casex(ST)//STC CCR,@ERd
8'b????_???1:c_vect( 52'b_1_00_1001_00000_00_0_0_0_0_0_0_0_0_00_0_10_00_000_0_00_0_1_00_00_0_0111_000_010);
endcase // ST
8'h6B:
case (irword[39:36])
4'b0000://LDC @aa:16,CCR
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0011_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_011);
endcase // ST
4'b0010://LDC @aa:24,CCR
casex(ST)//STC
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0101_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_100);
endcase // ST
4'b1000://STC CCR,@(aa:16)
casex(ST)//STC
8'b????_???1:c_vect( 52'b_1_00_1001_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0011_000_011);
endcase // ST
4'b1010://STC CCR,@(aa:24)
casex(ST)//STC
8'b????_???1:c_vect( 52'b_1_00_1001_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_1_00_00_0_0101_000_100);
endcase // ST
endcase
8'h6F:
if (!irword[39])//// LDC @(d:16,ERs),CCR
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0110_011_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_011);
endcase // ST
else//STC CCR,@(d:16,ERd)
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_1001_00000_00_0_0_0_0_0_0_0_0_00_0_10_00_000_0_00_0_1_00_00_0_0111_011_011);
endcase // ST
default: $stop;
endcase
// default: $stop;
endcase
4'b0010: //STC CCR,Rd
casex(ST) //
8'b????_???1:c_vect( 52'b_1_00_1001_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011: // LDC Rs,CCR
casex(ST) //
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0100: // ORC #xx:8,CCR
casex(ST) //
8'b????_???1:c_vect( 52'b_1_01_1001_00111_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0101: // XORC #xx:8,CCR
casex(ST) //
8'b????_???1:c_vect( 52'b_1_01_1001_01000_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0110: // ANDC #xx:8,CCR
casex(ST) //
8'b????_???1:c_vect( 52'b_1_01_1001_00110_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0111: // LDC #xx:8,CCR
casex(ST) //
8'b????_???1:c_vect( 52'b_1_01_0000_00001_00_0_0_0_0_0_0_0_1_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1000: //ADD.B Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00010_00_0_0_1_1_1_1_1_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001: // ADD.W Rs,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00010_01_0_0_1_1_1_1_1_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1010:
casex(irword[55])
1'b0://INC.B.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0010_00010_00_0_0_0_1_1_1_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1:// ADD.L Ers,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00010_10_0_0_1_1_1_1_1_0_00_0_01_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default $stop;
endcase
4'b1011:
casex(irword[55:52])
4'b0000 :// ADDS.L #1,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0010_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0101://INC.W #1,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0010_00010_01_0_0_0_1_1_1_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0111://INC.L #1,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0010_00010_10_0_0_0_1_1_1_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1101://INC.W #2,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0011_00010_01_0_0_0_1_1_1_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1111://INC.L #2,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0011_00010_10_0_0_0_1_1_1_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1000://ADDS.L #2,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0011_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001://ADDS.L #4,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0100_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // STcase
// default:$stop;
endcase
4'b1101: // MOV.W. Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00001_01_0_1_0_1_1_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1100: // MOV.B. Rs,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00001_00_0_1_0_1_1_0_0_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1110: // ADDX.B. Rs,Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_00_0000_00100_00_0_0_1_1_1_1_1_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1111: //MOV.L Ers,ERd
casex(ST) //
8'b????_???1:c_vect( 52'b_1_00_0000_00001_10_0_1_0_1_1_0_0_0_00_0_01_00_000_1_10_0_0_00_00_0_0000_000_001);
endcase // ST
default: begin $display("[11:8] undefined command error"); $stop; end
endcase // IR[11:8]
4'b0001: casex(irword[59:56])
4'b0000:
casex(irword[55:52])
4'b1000://SHAL.B, Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01111_00_0_0_0_1_1_1_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001://SHAL.W,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01111_01_0_0_0_1_1_1_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011://ShAL.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01111_10_0_0_0_1_1_1_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0000://SHLL.B, Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10001_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001://SHLL.W,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10001_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011://SHLL.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10001_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default: $stop;
endcase //
4'b0001:
casex(irword[55:52])
4'b1000://SHAR.B, Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10000_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001://SHAR.W,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10000_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011://ShAR.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10000_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0000://SHLR.B, Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10010_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001://SHLR.W,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10010_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011://SHLR.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_10010_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default: $stop;
endcase //
4'b0010:
casex(irword[55:52])
4'b1000://ROTL.B.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01011_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001://ROTL.W.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01011_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011://ROTL.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01011_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0000://ROTXL.B.Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01101_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001://ROTXL.W.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01101_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011://ROTX.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01101_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default: $stop;
endcase //
4'b0011:
casex(irword[55:52])
4'b1000://ROTR.B.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01100_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001://ROTR.W.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01100_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011://ROTR.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01100_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0000://ROTXR.B.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01110_00_0_1_0_1_1_0_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001://ROTXR.W.Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01110_01_0_1_0_1_1_0_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011://ROTXR.L,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_01110_10_0_1_0_1_1_0_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default: $stop;
endcase //
4'b0100: // OR.B. Rs,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00111_00_0_1_0_1_1_0_0_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0101: // XOR.B. Rs,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01000_00_0_1_0_1_1_0_0_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0110: // AND.B. Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00110_00_0_1_0_1_1_0_0_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0111:
casex (irword[55:52])
4'b0000://NOT.B Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_11000_00_0_1_0_1_1_0_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001: //NOT.W Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_11000_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011: //NOT.L Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_11000_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1000: //NEG.B Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_10111_00_0_0_1_1_1_1_1_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001: //NEG.W Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_10111_01_0_0_1_1_1_1_1_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1011: //NEG.L Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_10111_10_0_0_1_1_1_1_1_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1101: //EXTS.W.Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01001_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
endcase // ST
4'b1111: //EXTS.L ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01001_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
endcase // ST
4'b0101: //EXTU.W Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01010_01_0_1_0_1_1_0_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
endcase // ST
4'b0111: //EXTU.L Erd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_01010_10_0_1_0_1_1_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
endcase // ST
default: begin $display("[11:8] undefined command error"); $stop; end
endcase //
4'b1000: // SUB.B. Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00011_00_0_0_1_1_1_1_1_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001: // SUB.W. Rs,Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0000_00011_01_0_0_1_1_1_1_1_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1010:
casex (irword[55])
1'b0:// DEC.B.Rd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0101_00010_00_0_0_0_1_1_1_0_0_00_0_00_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
1'b1:// SUB.L Ers,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00011_10_0_0_1_1_1_1_1_0_00_0_01_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
endcase
4'b1011: //
casex (irword[55:52])
4'b0000://SUBS.L #1,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0101_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0101://DEC.W #1,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0101_00010_01_0_0_0_1_1_1_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1101://DEC.W #2,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0110_00010_01_0_0_0_1_1_1_0_0_00_0_00_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0111://DEC.L #1,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0101_00010_10_0_0_0_1_1_1_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1111://DEC.L #2,ERd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0110_00010_10_0_0_0_1_1_1_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1000: //SUBS.L #2,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0110_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1001: //SUBS.L #4,ERd
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0111_11001_10_0_0_0_0_0_0_0_0_00_0_00_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
default: $stop;
endcase
4'b1100: // CMP.B Rs,Rd
casex(ST) //
8'b????_???1:c_vect( 52'b_1_00_0000_00011_00_0_0_1_1_1_1_1_0_00_0_01_00_000_0_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase
4'b1101: // CMP.W Rs,Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_00_0000_00011_01_0_0_1_1_1_1_1_0_00_0_01_00_000_0_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase
4'b1110://SUBX Rs,Rd
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00101_00_0_0_1_1_1_1_1_0_00_0_01_00_000_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b1111: // CMP.L Ers,ERd
casex(ST) //
8'b????_???1: c_vect( 52'b_1_00_0000_00011_10_0_0_1_1_1_1_1_0_00_0_10_10_000_0_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase
default: begin $display("[11:8] undefined command error"); $stop; end
endcase // IR[11:8]
4'b0010: // MOV.B @aa:8,Rd
casex(ST) //
8'b????_???1: c_vect( 52'b_0_00_0000_00000_10_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_1000_00000_00_0_1_0_1_1_0_0_0_00_0_00_00_001_1_00_0_0_00_00_0_0000_000_001);
default: $stop;
endcase
4'b0011: // MOV.B Rs,@aa:8
casex(ST) //
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_1_0_1_1_0_0_0_00_0_00_01_000_0_00_0_1_00_00_0_0001_000_001);
default: $stop;
endcase
4'b0100: // BCC disp8
casex(ST)
8'b????_???1:
c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_11_0_1100_001_001);
default: $stop;
endcase // ST
default: begin $display("[11:8] undefined command error"); $stop; end
// endcase // IR[11:8]
4'b0101: casex(irword[59:56])
4'b0000: // MULXU.B Rs,Erd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_??1?: c_vect( 52'b_1_00_1010_00000_01_0_0_0_1_1_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0010: // MULXU.W Rs,Erd
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_01_00_000_0_01_0_0_00_00_0_0000_000_000);
8'b????_??1?: c_vect( 52'b_1_00_1010_00000_10_0_0_0_1_1_0_0_0_00_0_01_00_000_1_10_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0001: //DIVXU.B Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00001_00_0_0_0_0_1_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_01_0_0_0_0_0_0_0_0_00_0_01_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_0_00_1010_00001_01_0_0_0_0_0_0_0_0_00_0_01_00_000_0_01_0_0_00_00_0_0000_000_000);
8'b????_1???:c_vect( 52'b_1_00_1010_00000_01_0_0_0_0_0_0_0_0_00_0_01_00_000_1_01_0_0_00_00_0_0000_000_001);
default: $stop;
endcase // ST
4'b0011: // DIVXU.W Rs,Erd
casex(ST)
8'b????_???1:c_vect( 52'b_0_00_0000_00001_00_0_0_0_0_1_0_0_0_00_0_01_00_000_0_01_0_0_00_00_0_0000_000_000);
8'b????_??1?:c_vect( 52'b_0_00_0000_00000_10_0_0_0_0_0_0_0_0_00_0_01_00_000_0_01_0_0_00_00_0_0000_000_000);
8'b????_?1??:c_vect( 52'b_0_00_1010_00001_10_0_0_0_0_0_0_0_0_00_0_01_00_000_0_10_0_0_00_00_0_0000_000_000);
8'b????_1???:c_vect( 52'b_1_00_1010_00000_10_0_0_0_0_0_0_0_0_00_0_01_00_000_1_10_0_0_00_00_0_0000_000_001);
endcase // ST
4'b0100: // RTS
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00001_10_0_0_0_0_0_0_0_0_00_0_11_00_000_0_10_0_0_00_00_0_1001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0100_00010_00_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_10_0_1010_000_000);
default: $stop;
endcase // ST
4'b0101: // BSR d:8
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_1100_001_001);
default: $stop;
endcase // ST
4'b0110: // RTE
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00001_10_0_0_0_0_0_0_0_0_00_0_11_00_000_0_10_0_0_00_00_0_1001_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0100_00010_00_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_1_01_0_00_00_000_0_00_0_0_10_10_0_1010_000_000);
default: $stop;
endcase // ST
4'b1000: // BCC disp16
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_11_0_1100_010_010);
default: $stop;
endcase // S
4'b1001: // JMP @Rn
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_01_0_0110_000_000);
default: $stop;
endcase // ST
4'b1010: // JMP @aa:24
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_01_0_1011_000_000);
default: $stop;
endcase // ST
4'b1011: // JMP @@aa:8
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_00_0_1000_000_000);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_?1??: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_01_0_1010_000_000);
default: $stop;
endcase // ST
4'b1100://BSR d:16
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_1100_010_010);
default: $stop;
endcase // ST
4'b1101: // JSR @Ern
casex(ST)
8'b????_???1:c_vect( 52'b_1_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_0110_000_001);
default: $stop;
endcase // ST
4'b1110: //JSR @aa:24
casex(ST)
8'b????_???1: c_vect( 52'b_1_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_1011_000_010);
default: $stop;
endcase // ST
4'b1111://JSR @aa:8
casex(ST)
8'b????_???1: c_vect( 52'b_0_00_0111_00010_10_0_0_0_0_0_0_0_0_00_0_11_00_100_1_10_1_1_10_01_1_0000_000_001);
8'b????_??1?: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_00_0_1000_000_000);
8'b????_?1??: c_vect( 52'b_0_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_00_00_0_0000_000_000);
8'b????_1???: c_vect( 52'b_1_00_0000_00000_00_0_0_0_0_0_0_0_0_00_0_00_00_000_0_00_0_0_10_01_0_1010_000_000);
default: $stop;
endcase // ST
default: begin $display("[11:8] undefined command error"); $stop; end
endcase // IR[11:8]
endcase // inst
end
end
// State Counter
always @ (posedge clock) begin
if (sync_reset ==1'b1) ST<=8'h00;
else if (end_state== 1'b1) ST<=8'h00;
else begin
if (stop_state) ST<=ST;
else casex(ST)
8'b0000_0000: ST<=8'b0000_0001;
8'b????_???1: ST<=8'b0000_0010;
8'b????_??1?: ST<=8'b0000_0100;
8'b????_?1??: ST<=8'b0000_1000;
8'b????_1???: ST<=8'b0001_0000;
8'b???1_????: ST<=8'b0010_0000;
8'b??1?_????: ST<=8'b0100_0000;
8'b?1??_????: ST<=8'b1000_0000;
8'b1???_????: ST<=8'b0000_0000;
endcase
end
end
// Bus State Control
always @ (posedge clock) begin
if (sync_reset) bus_state <=2'b00;
else begin
case (bus_state)
2'b00: if (!sync_reset) bus_state<=2'b01;
2'b01: if (end_state) bus_state<=2'b11;
2'b11: if (int_latch && end_state) bus_state<=2'b10;
2'b10: if (end_state) bus_state<=2'b11;
endcase
end
end
// interrupt controller ; interim, timing is different from original.
always @(posedge clock) begin
if (sync_reset) int_latch<=1'b0;
else if (i_bit) int_latch<=1'b0;
else if (int_req2) int_latch<=1'b1;
// else if (int_icb) int_latch<=1'b1;
end
always @(posedge clock) begin
if (sync_reset) int_req2_ack<=1'b0;
else if (int_latch && int_req2 && !int_req2_ack) int_req2_ack<=1'b1;
else if (int_req2_ack && bus_state==2'b10 && ST==8'b0000_0100) int_req2_ack<=1'b0;
end
endmodule
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